參數(shù)資料
型號(hào)： TMS34020
廠商： Texas Instruments, Inc.
英文描述： GRAPHICS PROCESSORS
中文描述： 圖形處理器
文件頁數(shù)： 66/82頁
文件大小： 1359K
代理商： TMS34020
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
66
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
local bus timing: bus control inputs (see Figure 41)
NO.
PARAMETER
’34020-32
’34020A-32
’34020A-40
UNIT
MIN
MAX
tQ+15
tQ+15
MIN
MAX
tQ+13.5
tQ+13.5
57
td(CK2
↑
-ALL)
td(CK1
↓
-ALH)
Delay time, ALTCH low after LCLK2
↑
Delay time, ALTCH high after LCLK1
↓
ns
58
ns
59
td(CK1
↑
-LAV)
Delay time, LAD0–LAD31 address valid after
LCLK1
↑
tQ+22
tQ+20
ns
60
th(LAV-CK2L)
Hold time, LAD0–LAD31 address valid after
LCLK2 low
tQ–15+ s
tQ–12+ s
ns
61
td(CTNV-LAD)
Delay time, LAD0–LAD31 driven after earlier
of DDIN
↓
or CAS
↑
or TR/QE
↑
tQ–5+ s
tQ–5+ s
ns
62
th(LAV-CTV)
Hold time, LAD0–LAD31 read data valid after
earlier of DDIN low or RAS, CAS, or TR/QE
high
0
2
ns
63
td(CK2
↓
-LAV)
Delay time, LAD0–LAD31 data valid after
LCLK2
↓
(write)
tQ+22+ s
tQ+20+ s
ns
64
th(CK2L-LAV)
Hold time, LAD0–LAD31 data valid after
LCLK2 low (write)
tQ–15
tQ–13.5
ns
65
td(CK1
↑
-RCV)
Delay time, RCA0–RCA12 row address valid
after LCLK1
↑
tQ+22
tQ+20
ns
66
td(CK2
↓
-RCV)
Delay time, RCA0–RCA12 column address
valid after LCLK2
↓
tQ+22+ s
tQ+20+ s
ns
67
th(RCV-CK2L)
Hold time, RCA0–RCA12 address valid after
LCLK2 low
tQ–15
tQ–12
ns
68
td(CK1
↑
-DIH)
td(CK1
↓
-DIL)
td(CK1
↑
-DOL)
td(CK1
↓
-DOH)
td(CK2
↓
-DOL)
Delay time, DDIN high after LCLK1
↑
Delay time, DDIN low after LCLK1
↓
Delay time, DDOUT low after LCLK1
↑
Delay time, DDOUT high after LCLK1
↓
Delay time, DDOUT low after LCLK2
↓
tQ+15
tQ+15
tQ+15
tQ+15
tQ+15+ s
tQ+13.5
tQ+13.5
tQ+13.5
tQ+13.5
tQ+13.5+ s
ns
69
ns
70
ns
71
ns
72
ns
73
tsu(LAV-AL
↓
)
Setup time, LAD0–LAD31 data valid before
ALTCH
↓
tQ–16
tQ–13
ns
74
ten(DAV-DIH)
Enable time, data valid after DDIN high
(see Note 4)
2tQ–20
2tQ–17
ns
75
tdis(DAV-DIL)
Disable time, data high-impedance after DDIN
low (see Note 4)
tQ–12+ s
tQ–10+ s
ns
e
th(REL-RCV)
Hold time, RAS valid low after column address
valid
3tQ – 22
3tQ – 12
ns
f
th(CEL-RCV)
Hold time, CAS valid low after column address
valid
3tQ – 22
3tQ – 12
ns
g
th(WEH-RCV)
Hold time, WE valid low after column address
valid
4tQ – 22 + s
4tQ – 18 + s
ns
h
th(LAV-WEH)
Hold time, LAD data valid after WE valid high
tQ – 15
tQ – 12
ns
These values are derived from characterization data and are not tested.
NOTE 4: DDIN is used to control LAD bus buffers between the TMS34020 and local memory. Parameter 74 references the time for these data
buffers to go from the high-impedance state to an active level. Parameter 75 references the time for the buffers to go from an active level
to the high-impedance state.
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