參數(shù)資料
型號： TMS34020
廠商： Texas Instruments, Inc.
英文描述： GRAPHICS PROCESSORS
中文描述： 圖形處理器
文件頁數(shù)： 33/82頁
文件大小： 1359K
代理商： TMS34020
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
33
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Q4
Q1
Q2
Q3
Q4*
Q1
Q2
Q3
Q4
Q1
All-Zero Address
Zero Address
Color Register Data
GI
LAD
CAMD
RCA
ALTCH
RAS
CAS
WE
TR/QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
*See clock stretch, page 21.
Figure 10. Load-Color-Latch Cycle
This special 1M VRAM control cycle is generated by the VLCOL instruction and is indicated by CAS, WE,
TR/QE, and SF high at the falling edge of RAS and SF high at the falling edge of CAS. The data in the COLOR1
register is output on LAD to be written to a special register on the VRAM that is used in subsequent cycles
requiring a color latch. During the address portion of the cycle, the status on LAD0–LAD3 indicates a color-mask
load is being performed (status code = 0111). Although CAMD, PGMD, and SIZE16 are ignored on this cycle,
they should be held at valid levels as shown.
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