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參數(shù)資料
| 型號： | TMS34020 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | GRAPHICS PROCESSORS |
| 中文描述： | 圖形處理器 |
| 文件頁數(shù)： | 31/82頁 |
| 文件大?。?/td> | 1359K |
| 代理商： | TMS34020 |
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TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
31
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Row
Column (S=0)
Column (S=1)
Q4
Q1
Q2
Q3
Q4*
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Low Address
Address Subcycle
Data Transfer
Subcycle
Data Transfer
Subcycle
High Address
Data Low
Data High
Data High
Data Low
LCLCK1
LCLCK2
GI
LAD0–LAD15
LAD16–LAD31
CAMD
RCA
ALTCH
RAS
CAS0
CAS1
CAS2
CAS3
WE
TR/QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
*See clock stretch, page 21.
Figure 8. Dynamic Bus Sizing, Write Cycle
Write accesses to 16-bit memory are performed by swapping the data on upper and lower words of the LAD
bus and exchanging data on CAS0 and CAS1 for data on CAS2 and CAS3, respectively. This is illustrated in
the above example where the TMS34020 is writing the upper 24 bits (LAD8–LAD31) of data to memory. During
the first cycle, data is placed on LAD0–LAD31 as in a normal write. The sampling of SIZE16 low during the first
access indicates that this is 16-bit-wide memory, so the TMS34020 swaps data on the upper and lower halves
of the LAD bus. Notice that during the first cycle CAS0 is inactive (since this byte was not selected) and during
the second cycle CAS2 is inactive due to the exchange of CAS0 for CAS2 and CAS1 for CAS3.
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