
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
55
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
timing parameter symbology
Timing parameter symbols used herein were created in accordance with JEDEC Standard 100. In order to
shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows:
A
AD
AL
BC
HA5–HA31 and HBS0–HBS3
LAD0–LAD31 and RCA0–RCA12
ALTCH
Any of the bus control input signals
(LRDY, PGMD, SIZE16, or BUSFLT)
CAS0–CAS3
LCLK1 and LCLK2
LCLK1
LCLK2
CLKIN
CAMD
HCS
Any of the bus control output signals
(ALTCH, CAS0–CAS3, RAS, WE,
TR/QE, HOE, or HDST)
DDIN
DDOUT
EMU0, EMU1, EMU2
HINT
HSYNC, VSYNC, CSYNC/HBLNK, or
CBLNK/VBLNK
GI
LA
LINT
OE
GI
LAD0–LAD31
LINT1, LINT2
HOE
CE
CK
CK1
CK2
CKI
CM
CS
CT
RC
RD
RE
RQ
RS
RY
RCA0–RCA12
HREAD
RAS
R0 or R1
RESET
HRDY
S
SC
SCK
SF
SG
ST
TR
VCK
WR
HSYNC, VSYNC, or CSYNC
EMU3
SCLK
SF
Any output signal
HDST
TR/QE
VCLK
HWRITE
DI
DO
EM
HI
HS
Lowercase subscripts and their meaning are:
a
c
d
h
su
t
w
access time
cycle time (period)
delay time
hold time
setup time
transition time
pulse duration (width)
The following letters and symbols and their meaning are:
H
L
NV
V
Z
↑
↓
D
High
Low
Not valid
Valid
High impedance
No longer low
No longer high
Driven
s = 0
For (i)
TMS34020
(ii) TMS34020A, if CSE bit in CONFIG register is
set to 0
(iii) TMS34020A, if CSE bit in CONFIG register is set to
1 andthe cycle is notstretched. See page 21.
s = t
Q
For TMS34020A, if CSE bit in CONFIG register is set to 1
andthe cycle is stretched. See page 21.