
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
61
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
host interface timing requirements (see Figure 36 and Note 3)
NO.
PARAMETER
’34020-32
’34020A-32
’34020A-40
UNIT
MIN
MAX
MIN
MAX
23
tsu(AV-CS
↓
)
th(CSL-AV)
tw(CSH)
tw(RDH)
tw(WRH)
tsu(RDH-WR
↓
)
tsu(WRH-RD
↓
)
tw(RDL)
tw(WRL)
tsu(CSL-WR
↑
)
tsu(RDL-CK2
↓
)
tsu(WRH-CK2
↓
)
th(CK2
↓
-RDH)
th(CK2
↓
-WRL)
tsu(RDH-CK2
↓
)
tsu(CSL-RD
↑
)
Setup time of address prior to HCS
↓
Hold time of address after HCS low
12
10
ns
24
12
10
ns
25
Pulse duration of HCS high
28
25
ns
26
Pulse duration of HREAD high
28
25
ns
27
Pulse duration of HWRITE high
Setup time, HREAD high to HWRITE
↓
Setup time, HWRITE high to HREAD
↓
28
25
ns
28
28
25
ns
29
28
25
ns
30
Pulse duration of HREAD low
18
15
ns
31
Pulse duration of HWRITE low
Setup time, HCS low to HWRITE
↑
Setup time, later of HCS low or HREAD low to LCLK2
↓
Setup time, later of HWRITE high or HCS high to LCLK2
↓
Hold time, HREAD high after LCLK2
↓
Hold time, HWRITE low after LCLK2
↓
Setup time, HREAD high to LCLK2
↓
, prefetch read mode
Setup time, HCS low to HREAD
↑
18
15
ns
32
18
30
30
0
0
30§
15
25
25
0
0
25§
ns
33
ns
34
ns
35
ns
36
ns
37
ns
38
18
15
ns
Setup time to insure recognition of input on this clock edge.
Hold time required to assure response on next clock edge. These values are based on computer simulation and are not tested.
§When the TMS34020 is set for block reads, use the deassertion of HREAD to request a local memory cycle at the next sequential address location.
NOTE 3: Although HCS, HREAD, and HWRITE can be totally asynchronous to the TMS34020, cycle responses to the signals are determined
by local memory cycles.
HA0–HA27
HBS0–HBS
3
23
25
35
33
37
29
24
28
31
27
34
36
32
26
38
30
HCS
HREAD
HWRITE
LCLK2
Figure 36. Host Interface Timing Requirements