參數(shù)資料
型號： TMS34020
廠商： Texas Instruments, Inc.
英文描述： GRAPHICS PROCESSORS
中文描述： 圖形處理器
文件頁數(shù)： 18/82頁
文件大小： 1359K
代理商： TMS34020
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
18
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
status codes
Status codes are output on LAD0–LAD3 at the time of the falling edge of ALTCH and may be used to determine
the type of cycle that is being initiated. The following table lists the codes and their respective meanings.
CODE
STATUS
TYPE
0000
Coprocessor Code
0001
Emulator Operation
Other
0010
Host Cycle
(00XX)
0011
DRAM Refresh
0100
Video-generated DRAM Serial Register Transfer
0101
CPU-generated VRAM Serial Register Transfer
VRAM
0110
Write Mask Load
(01XX)
0111
Color Latch Load
1000
Data Access
1001
Cache Fill
1010
Instruction Fetch
1011
Interrupt Vector Fetch
CPU
1100
Bus Locked Operation
(1XXX)
1101
Pixel Operation
1110
Block Write
1111
Reserved
dynamic bus sizing
The TMS34020 supports dynamic bus sizing between 16 and 32 bits on any local memory access. Any
port/memory that is only 16 bits wide must assert SIZE16 low during Q1 (to be valid at the start of Q2) of the
bus cycle accessing the even memory word (LAD4 = 0) corresponding to its address.The TMS34020 then
performs another memory access to the next 16-bit (odd) word in memory. The TMS34020 samples the SIZE16
pin at the start of Q2 in the second cycle (access to odd word address) to determine to which half of the LAD
bus the port or memory is aligned. If the port is on LAD0–LAD15, the SIZE16 input should be low during the
second cycle access (odd word); otherwise, if the port is on LAD16–LAD31, the SIZE16 input must be high at
this time. The TMS34020 always performs two memory cycles to access the 16-bit wide memories, even when
attempting only a 16-bit transfer.
The TMS34020 outputs the four CAS strobes and LAD bus initially aligned for a 32-bit bus. If the memory is 16
bits wide, the two most significant CAS strobes are swapped with the two least significant strobes when it
accesses the second word, and the halves of the LAD bus are also swapped; therefore, 16-bit memories need
to respond only to the two CAS strobes corresponding to the upper or lower 16 bits of the LAD bus to which they
are connected.
Note that devices connected to LAD0–LAD15 transfer the least significant word during the first cycle and the
most significant word during the second cycle. Data accesses on LAD16–LAD31 transfer the most significant
word first, then the least significant word.
The second memory cycle forced by the SIZE16 pin is performed as a page-mode access if PGMD was low
during the first access. A read-write cycle to 16-bit page-mode memory requires five bus cycles that occur as
address, read0, read1, write0, write1. If a 16-bit transfer is interrupted due to a bus fault, the restart causes the
entire access to be restarted.
For memory that supports page-mode accesses (PGMD low), SIZE16 is sampled during each access to
memory. If SIZE16 is high on the even-word access, then a 32-bit transfer occurs over LAD0–LAD31. If SIZE16
is low on the even-word access (16-bit wide memory), then it is sampled again on the odd-word access to
determine to which half of the LAD bus the memory is connected (low for connection to LAD0–LAD15 or high
for connection to LAD16–LAD31).
相關(guān)PDF資料
PDF描述
TMS3450NL LED DUPLEX DIGITAL RADIO CLOCK
TMS3471CFS 780- 】 488-pixel ccd image sensor
TMS3471 2/3-INCH NTSC TIMER
TMS3473 PARALLEL DRIVER
TMS370C036A 8-BIT MICROCONTROLLER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TMS3450NL 制造商:Rochester Electronics LLC 功能描述:- Bulk
TMS3459BNL 制造商:Panasonic Industrial Company 功能描述:IC
TMS3471C 制造商:Rochester Electronics LLC 功能描述:- Bulk
TMS3472ADW 制造商:Rochester Electronics LLC 功能描述:- Bulk
TMS3637D 制造商:Rochester Electronics LLC 功能描述:- Bulk
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*