參數(shù)資料
型號： TMS34020
廠商： Texas Instruments, Inc.
英文描述： GRAPHICS PROCESSORS
中文描述： 圖形處理器
文件頁數(shù)： 27/82頁
文件大?。?/td> 1359K
代理商： TMS34020
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
27
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
LCLCK1
LCLCK2
GI
LAD
CAMD
RCA
ALTCH
RAS
CAS
WE
TR/QE
SF
DDIN
DDOUT
LRDY
PGMD
SIZE16
BUSFLT
R0
R1
Q4
Q1
Q2
Q3
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Address
Row
1st Column
2nd Column
Address Subcycle
Data Transfer
Subcycle
Data Transfer
Subcycle
Data Out 1
Data Out 2
Q4*
Standard Memory Write Cycle
Page-Mode Write
*See clock stretch, page 21.
NOTE A: LRDY, PGMD, SIZE16, and BUSFLT are not sampled on subsequent page-mode cycle accesses to 32-bit-wide memory space.
Figure 4. Local Memory Write Cycle Timing (With Page Mode)
During the address output to the LAD bus by the TMS34020, the least significant four bits (LAD0–LAD3) contain
a bus-status code. PGMD low at the start of Q2 after RAS low indicates that this memory supports page-mode
operation. LRDY high at the start of Q2 after RAS low indicates that the cycle can continue without inserting wait
states.
DDOUT remains low after the initial address output on LAD (during Q4 after RAS goes low), indicating that a
memory write cycle is about to take place.
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