參數(shù)資料
型號(hào)： TMS34020
廠商： Texas Instruments, Inc.
英文描述： GRAPHICS PROCESSORS
中文描述： 圖形處理器
文件頁數(shù)： 68/82頁
文件大?。?/td> 1359K
代理商： TMS34020
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
68
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
local bus timing: RAS, CAS0–CAS3, WE, TR/QE, and SF
NO.
PARAMETER
’34020-32
’34020A-32
’34020A-40
UNIT
MIN
MAX
MIN
MAX
62
th(LAV-CTV)
Hold time, LAD0–LAD31 read data
valid after earlier of DDIN, LCLK2 low
or RAS, CAS, or TR/QE high
Delay time, RAS low after LCLK1
↓
Delay time, RAS high after LCLK1
↓
Delay time, CAS low after LCLK1
↑
Delay time, CAS high after LCLK1
↓
Delay time, WE low after LCLK2
↓
Delay time, WE high after LCLK1
↓
Delay time, TR/QE low after LCLK2
↓
Delay time, TR/QE high after LCLK1
↓
Delay time, SF valid after LCLK1
↑
Delay time, SF valid after LCLK2
↓
0
2
ns
76
td(CK1
↓
-REL)
td(CK1
↓
-REH)
td(CK1
↑
-CEL)
td(CK1
↓
-CEH)
td(CK2
↓
-WEL)
td(CK1
↓
-WEH)
td(CK2
↓
-TRL)
td(CK1
↓
-TRH)
td(CK1
↑
-SFV)
td(CK2
↓
-SFV)
tQ+12+ s
tQ+12
tQ+12
tQ+12
tQ+15+ s
tQ+15
tQ+15+ s
tQ+15
tQ+22
tQ+22+ s
tQ+10+ s
tQ+10
tQ+10
tQ+10
tQ+13.5+ s
tQ + 15
tQ+13.5+ s
tQ+13.5
tQ+20
tQ+20+ s
ns
77
ns
78
ns
79
ns
80
ns
81
ns
82
ns
83
ns
84
ns
85
ns
86
td(CK2
↓
-SFZ)
Delay time, SF high-impedance after
LCLK2
↓
tQ+22
tQ+20
ns
87
tsu(ADV-RE
↓
)
Setup time, row address valid before
RAS
↓
2tQ– 22
2tQ– 20
ns
88
th(ADV-REL)
Hold time, row address valid after RAS
low
tQ– 5+ s
tQ– 5+ s
ns
89
tsu(RCV-CE
↓
)
Setup time, column address valid
before CAS
↓
tQ– 22
tQ– 20
ns
90
th(RCV-CEH)
Hold time, column address valid after
CAS high
tQ– 15
tQ– 13.5
ns
91
tsu(CAV-CE
↓
)
Setup time, write data valid before
CAS
↓
Hold time, write data valid after CAS
↑
Access time, data in valid after RAS
low (assuming maximum transition
time)
Access time, data in valid after CAS
↓
Access time, data in valid after column
address valid
tQ– 22
tQ– 20
ns
92
th(CAV-CE
↑
)
tQ– 15
tQ– 13.5
ns
93
ta(LAV-REL)
4tQ– 8+ s
4tQ– 8+ s
ns
94
ta(LAV-CEL)
2tQ– 8
2tQ–8
ns
95
ta(LAV-RCV)
3tQ – 17
3tQ – 2
ns
96
ta(LAV-LAV)
Access time, data in valid after
address valid on LAD bus
6tQ – 17 + s
6tQ – 17 + s
ns
97
tsu(WEL-CE
↓
)
Setup time, write low before CAS
↓
(on write cycles)
tQ–15
tQ–13.5
ns
98
tw(REH)
tw(REL)
Pulse duration of RAS high
4tQ– 12+ s
4ntQ– 12+ s
′
§
4tQ– 10+ s
4ntQ– 4+ s
′
§
ns
99a
These values are derived from characterization data and are not tested.
Parameters 87 and 88 also apply to WE, TR/QE, and SF relative to RAS.
§s
′
is 2tQ since both the address cycle and the read data cycle of a read-modify-write will be stretched. See clock stretch, page 21.
n= number of GSP data cycles in in the memory access.
Pulse duration of RAS low
ns
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