參數(shù)資料
型號: TMS34020
廠商: Texas Instruments, Inc.
英文描述: GRAPHICS PROCESSORS
中文描述: 圖形處理器
文件頁數(shù): 58/82頁
文件大小: 1359K
代理商: TMS34020
TMS34020, TMS34020A
GRAPHICS PROCESSORS
SPVS004D – MARCH 1990 – REVISED NOVEMBER 1993
58
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
local bus timing: output clocks
NO.
PARAMETER
’34020-32
’34020A-32
’34020A-40
UNIT
MIN
MAX
MIN
MAX
11
tc(LCK)
tw(LCKH)
tw(CK1H)
tw(LCKL)
tw(CK1L)
tt(LCK)
th(CK1H-CK2L)
th(CK2H-CK1H)
th(CK1L-CK2H)
th(CK2L-CK1L)
th(CK1H-CK2H)
th(CK2H-CK1L)
th(CK1L-CK2L)
th(CK2L-CK1H)
Period of local clocks LCLK1, LCLK2
4tc(CKI)+ s
2tQ–15
2tQ–10
2tQ–15+ s
2tQ–10+ s
4tc(CKI)+ s
2tQ–13.5
2tQ–7
2tQ–13.5+ s
2tQ–7+ s
ns
12
Pulse duration, local clock high
ns
12a
Pulse duration, LCLK1 high
ns
13
Pulse duration, local clock low
ns
13a
Pulse duration, LCLK1 low
ns
14
Transition time, LCLK1 or LCLK2
15
13.5
ns
15
Hold time, LCLK2 low after LCLK1 high
tQ–15
tQ–15
tQ–15
tQ–13.5
tQ–13.5
tQ–13.5
tQ–13.5+ s
3tQ–13.5
3tQ–13.5+ s
3tQ–13.5+ s
3tQ–13.5+ s
ns
16
Hold time, LCLK1 high after LCLK2 high
ns
17
Hold time, LCLK2 high after LCLK1 low
ns
18
Hold time, LCLK1 low after LCLK2 low
tQ–15+ s
3tQ–15
3tQ–15+ s
3tQ–15+ s
3tQ–15+ s
ns
19
Hold time, LCLK2 high after LCLK1 high
ns
20
Hold time, LCLK1 low after LCLK2 high
ns
21
Hold time, LCLK2 low after LCLK1 low
ns
22
Hold time, LCLK1 high after LCLK2 low
ns
This is a functional minimum and is not tested. This parameter may also be specified as 4tQ.
These parameters are specified with 1.5-V timing levels (parameters 12 and 13 are specified with standard timing voltage levels as detailed on
page 54).
Q1
Q2
Q3
Q4*
Q1
Q2
Q3
Q4*
Q1
Q2
14
14
14
11
12
13
19
21
22
15
16
17
18
11
12
13
14
20
12a
13a
LCLK1
LCLK2
*See clock stretch, page 21.
NOTE A: Although LCLK1 and LCLK2 are derived from CLKIN, no timing relationship between CLKIN and the local clocks is to be assumed,
except the period of the local clocks is four times the period of CLKIN.
Figure 34. Local Bus Timing: Output Clocks
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