參數(shù)資料
型號(hào)： AMD-640
廠商： Advanced Micro Devices, Inc.
英文描述： 64-Bit Socket 7 Interface, Integrated Write back Cache Controller, System Memory Controller, and PCI Bus Controller.(64位系統(tǒng)控制器(包括高速緩沖存儲(chǔ)器控制器，系統(tǒng)存儲(chǔ)器控制器和PCI總線控制器))
中文描述： 64位Socket 7的接口，集成寫回高速緩沖存儲(chǔ)器控制器，系統(tǒng)內(nèi)存控制器和PCI總線控制器。（64位系統(tǒng)控制器（包括高速緩沖存儲(chǔ)器控制器，系統(tǒng)存儲(chǔ)器控制器和的PCI總線控制器））
文件頁數(shù)： 91/159頁
文件大?。?/td> 1900K
代理商： AMD-640
5-52
Functional Operation
AMD-640 System Controller Data Sheet
21090C/0—June 1997
Preliminary Information
If the buffer fills up before the write is complete, the
controller will deassert TRDY# until the buffer has written
some of its contents to memory and space is available for more
data. The write is completed when the memory bus becomes
available.
The L1 and L2 caches are snooped during the write to maintain
cache integrity. If the address hits a cache entry the cache data
is written and merged with the PCI data. The cache line is also
invalidated. To maintain data coherency, the write buffer
snoops PCI reads from memory. If read data hits the write
buffer, the read stalls by negating TRDY# until the write is
completed.
5.4.7
PCI Fast Back to Back cycles
The PCI specification allows fast back-to-back cycles to the
same target or to different targets. In the AMD-640 system
controller, this feature is controlled by the command register
(offset 05h–04h) for reads and the PCI configuration register
(offset 71h), bit 7 for writes. Offset 73h, bit 7 must be set for
slow decode if fast back-to-back is selected.
On same-target back-to-back cycles, the initiator is responsible
for preventing contention on TRDY#, DEVSEL#, STOP#, and
PERR#. The AMD-640 system controller deletes the idle cycle
prior to FRAME# and guarantees it will not produce any
contention when it is driving the PCI bus.
On different-target back-to-back cycles, the target is
responsible for preventing contention on TRDY#, DEVSEL#,
STOP#, and PERR#. When this option is selected the AMD-640
system controller will capture the address without an
intervening idle cycle. The AMD-640 system controller will
delay assertion of TRDY#, DEVSEL#, STOP#, and PERR# by
one clock to avoid contention. Avoiding contention in this
mode is more difficult because the capabilities of all targets in
the system must be known.
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