參數(shù)資料
型號： AMD-640
廠商： Advanced Micro Devices, Inc.
英文描述： 64-Bit Socket 7 Interface, Integrated Write back Cache Controller, System Memory Controller, and PCI Bus Controller.(64位系統(tǒng)控制器(包括高速緩沖存儲器控制器，系統(tǒng)存儲器控制器和PCI總線控制器))
中文描述： 64位Socket 7的接口，集成寫回高速緩沖存儲器控制器，系統(tǒng)內(nèi)存控制器和PCI總線控制器。（64位系統(tǒng)控制器（包括高速緩沖存儲器控制器，系統(tǒng)存儲器控制器和的PCI總線控制器））
文件頁數(shù)： 18/159頁
文件大小： 1900K
代理商： AMD-640
Overview
2-1
21090C/0—June 1997
AMD-640 System Controller Data Sheet
Preliminary Information
2
Overview
The AMD-640 system controller optimizes the interaction
between the processor, optional synchronous L2 cache, DRAM,
and the PCI bus with pipelined burst and concurrent
transactions. It provides 3-1-1-1-1-1-1-1 timing for both read and
write transactions with pipelined burst synchronous SRAMs
running at 66 MHz. The AMD-640 system controller includes
four cache lines (16 quadwords) of processor-to-DRAM or
cache-to-DRAM write buffering with concurrent writeback
capability to accelerate writeback and write miss cycles.
2.1
System
The local bus is a non-multiplexed bus based on AMD and Intel
processors. The AMD-640 system controller is capable of
performing I/O, single memory, and block memory
transactions. The AMD-640 system controller memory
controller can perform zero wait state memory reads and
writes using an advanced data buffering design. However, in
the event of a buffer miss, the memory controller inserts wait
states using the BRDY# wait procedure. The controller
responds only to I/O cycles within its configuration register
space and memory requests as defined in its configuration
registers. All cycle timing on the local bus is derived from the
CPU clock (CCLK). This same signal drives the AMD-640
system controller host clock (HCLK) input, from which the
controller derives all of its timing.
The AMD-640 system controller incorporates a high-
performance, flexible 64-bit DRAM controller that provides
the DRAM interface for either an AMD-K5 or AMD-K6
processor. The memory controller can perform zero wait state
reads or writes through the use of a prefetch read buffer or a
deep write buffer, respectively. It can address up to six banks
of DRAMs in various combinations of 1 Mbit, 2 Mbit, 4 Mbit,
and 16 Mbit by 32 or 64 bits, up to a total of 768 Mbytes. The
DRAM can be any combination of fast page mode (FPM)
DRAM, extended data out (EDO) DRAM, and Synchronous
DRAM (SDRAM). Synchronous DRAM allows zero wait state
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