參數(shù)資料
型號(hào)： AMD-640
廠商： Advanced Micro Devices, Inc.
英文描述： 64-Bit Socket 7 Interface, Integrated Write back Cache Controller, System Memory Controller, and PCI Bus Controller.(64位系統(tǒng)控制器(包括高速緩沖存儲(chǔ)器控制器，系統(tǒng)存儲(chǔ)器控制器和PCI總線控制器))
中文描述： 64位Socket 7的接口，集成寫回高速緩沖存儲(chǔ)器控制器，系統(tǒng)內(nèi)存控制器和PCI總線控制器。（64位系統(tǒng)控制器（包括高速緩沖存儲(chǔ)器控制器，系統(tǒng)存儲(chǔ)器控制器和的PCI總線控制器））
文件頁數(shù)： 69/159頁
文件大小： 1900K
代理商： AMD-640
5-30
Functional Operation
AMD-640 System Controller Data Sheet
21090C/0—June 1997
Preliminary Information
5.4
PCI Bus Controller
The AMD-640 system controller drives the 32-bit PCI bus
synchronously with the PCI clock (PCLK), which is a buffered
processor clock (HCLK) divided by two. It converts 64-bit
processor data to 32-bit PCI data and regenerates commands
with minimum overhead. A five-doubleword CPU-to-PCI post
write buffer enables the processor and PCI to operate
concurrently. The AMD-640 system controller converts
consecutive processor addresses to burst PCI cycles, employing
byte merging for optimal CPU-to-PCI throughput. Its unique
integration of PCI controller and DRAM controller functions
on one chip provides a fast 32-bit data link, crucial in achieving
zero-wait state buffer movement and sophisticated,
upgradeable buffer management schemes such as byte
merging. A 48-doubleword PCI-to-DRAM post write buffer and
a 26-doubleword DRAM-to-PCI prefetch buffer enable
concurrent PCI bus and DRAM/cache accesses during PCI
initiator transactions. 2-1-1-1 cache hit and 3-1-1-1 cache miss
timing provide a typical PCI bus initiator transfer rate of
greater than 100 Mbytes per second.
When the processor drives an I/O cycle to an address other
than the AMD-640 system controller’s configuration register
addresses, the controller passes the I/O cycle to the PCI bus.
The AMD-640 system controller posts the I/O cycle in one of its
write buffers. The controller does not respond to I/O cycles
driven by PCI initiators on the PCI bus. It allows these cycles
to complete on the PCI bus.
Transactions on the PCI bus consist of an address/control
phase followed by one or more data phases. Three signals
provide fundamental control of all PCI data transfers.
FRAME# is asserted by the initiator to indicate the beginning
and end of a transaction. IRDY# is asserted by the initiator to
indicate that it is ready to complete the current data phase.
TRDY# is asserted by the target to indicate that it is ready to
complete the current data phase.
When FRAME# and IRDY# are both inactive, the PCI bus is
idle. A transaction begins with an address phase, in which an
initiator simultaneously asserts FRAME# and issues the
address and bus command. The first data phase begins on the
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