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參數(shù)資料
| 型號： | AMD-640 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 64-Bit Socket 7 Interface, Integrated Write back Cache Controller, System Memory Controller, and PCI Bus Controller.(64位系統(tǒng)控制器(包括高速緩沖存儲器控制器，系統(tǒng)存儲器控制器和PCI總線控制器)) |
| 中文描述： | 64位Socket 7的接口，集成寫回高速緩沖存儲器控制器，系統(tǒng)內(nèi)存控制器和PCI總線控制器。（64位系統(tǒng)控制器（包括高速緩沖存儲器控制器，系統(tǒng)存儲器控制器和的PCI總線控制器）） |
| 文件頁數(shù)： | 72/159頁 |
| 文件大小： | 1900K |
| 代理商： | AMD-640 |
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Functional Operation
5-33
21090C/0—June 1997
AMD-640 System Controller Data Sheet
Preliminary Information
5.4.2
CPU-to-PCI (Write) Transactions
The AMD-640 system controller converts a full 64-bit
(quadword) CPU-to-PCI write into two consecutive 32-bit
(doubleword) PCI write cycles. It also features byte merging
(grouping smaller, consecutive CPU writes into doublewords)
and burst transactions (writing up to four doublewords in a
single PCI transaction). These features in combination
significantly reduce the bus bandwidth required to complete
PCI writes.
The AMD-640 system controller contains a five-doubleword
post write buffer between the processor and the PCI bus.
Every CPU-to-PCI write is stored in the buffer unless it is full,
allowing the processor to begin its next operation without
having to wait for the write to complete. When the PCI bus is
available, the AMD-640 system controller performs up to five
32-bit PCI writes to complete the transaction.
Byte Merging
Byte merging combines multiple CPU write cycles into a single
PCI transfer. The AMD-640 system controller monitors address
and byte enable signals to combine consecutive cycles
containing 1, 2, and 4-byte writes into a single 8-byte buffer.
The AMD-640 system controller does not allow non-contiguous
byte merging. To merge bytes, the second write must be to a
subsequent byte location in the 8 byte line. For example, if the
first write is a byte write to byte location 3, only subsequent
writes to byte locations 4-7 can be merged. If a write is made to
locations 0-2, it will be posted to the next write buffer. In
addition, the AMD-640 system controller does not allow re-
ordering or over-writing merges. This is necessary to maintain
support for strong write ordering, in which writes are placed
on the PCI bus in the order they are received from the
processor.
The AMD-640 system controller also supports byte merging for
writes to the video/frame buffer area.
Burst Cycles
The AMD-640 system controller writes all of its buffer contents
in a single PCI transaction when the bus becomes available. In
this way, consecutive CPU-to-PCI writes, whether two full
quadwords or several smaller transactions combined through
byte merging, are performed in a single PCI transaction.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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