參數(shù)資料
型號： AMD-640
廠商： Advanced Micro Devices, Inc.
英文描述： 64-Bit Socket 7 Interface, Integrated Write back Cache Controller, System Memory Controller, and PCI Bus Controller.(64位系統(tǒng)控制器(包括高速緩沖存儲器控制器，系統(tǒng)存儲器控制器和PCI總線控制器))
中文描述： 64位Socket 7的接口，集成寫回高速緩沖存儲器控制器，系統(tǒng)內(nèi)存控制器和PCI總線控制器。（64位系統(tǒng)控制器（包括高速緩沖存儲器控制器，系統(tǒng)存儲器控制器和的PCI總線控制器））
文件頁數(shù)： 57/159頁
文件大?。?/td> 1900K
代理商： AMD-640
5-18
Functional Operation
AMD-640 System Controller Data Sheet
21090C/0—June 1997
Preliminary Information
Memory Detection
The AMD-640 system controller can accommodate different
memory sizes or types in different banks, but not within the
same bank or bank pair. A software or firmware mechanism
can be integrated into the BIOS that automatically detects the
type and size of the DRAM device in each bank. The
mechanism sets the Last Bank Populated to Bank 0 (offset 59h
bits 2-0, page 7-19), determines its type and size, sets the Bank
0 ending address (offset 5Ah, page 7-19), increments the Last
Bank Populated register, and performs the test on bank 1,
making sure the address range for bank 1 is above the range
determined for bank 0. The cycle is repeated for all populated
banks.
To determine the type of device, the mechanism configures the
target DRAM bank as EDO, enables it, writes data to it, reads
the data back, and compares the results. A match indicates the
presence of EDO DRAM, because standard DRAM does not
respond properly to the faster EDO access cycles. If the
comparison fails, the mechanism configures the bank as FPM
DRAM and performs a similar test. If this test also fails, a
somewhat more complex test can be run to determine if
SDRAM is present or a bank is empty. Refer to the BIOS guide
for more details. This procedure should be performed on eight
consecutive bytes to determine if different types of memory
devices are installed within a row. Any row containing
differing memory types should be disabled.
To determine the size of the device, the mechanism sets the
start address either at 0 or somewhere in the upper memory
area. Then, using the memory column size bits in the
corresponding configuration register (offsets 58h or 59h), the
mechanism selects the largest size and tests the memory at all
possible boundaries.
5.3.2
Error Correction Code
The AMD-640 system controller supports error correction code
(ECC) to check the integrity of transactions with system
memory. ECC, also referred to as Hamming code, corrects
single-bit and double-bit errors as well as some triple-bit
errors. ECC is enabled in offset 6Eh (page 7-30). The memory
modules must have parity bits to implement ECC.
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