參數(shù)資料
型號： AMD-640
廠商： Advanced Micro Devices, Inc.
英文描述： 64-Bit Socket 7 Interface, Integrated Write back Cache Controller, System Memory Controller, and PCI Bus Controller.(64位系統(tǒng)控制器(包括高速緩沖存儲器控制器，系統(tǒng)存儲器控制器和PCI總線控制器))
中文描述： 64位Socket 7的接口，集成寫回高速緩沖存儲器控制器，系統(tǒng)內(nèi)存控制器和PCI總線控制器。（64位系統(tǒng)控制器（包括高速緩沖存儲器控制器，系統(tǒng)存儲器控制器和的PCI總線控制器））
文件頁數(shù)： 59/159頁
文件大?。?/td> 1900K
代理商： AMD-640
5-20
Functional Operation
AMD-640 System Controller Data Sheet
21090C/0—June 1997
Preliminary Information
The AMD-640 system controller also contains a refresh counter
that provides 4096 refresh cycles on MA[11:0]. This permits
the use of DRAMs up to 16 Mbits in size. The refresh period is
derived by dividing HCLK by 16 (four-bit prescale) and a
refresh divisor based on the 8-bit value in offset 6Ah. The
refresh divisor can be calculated by multiplying the DRAM’s
required refresh period by the prescaled clock rate. For
example, in a system with HCLK = 66 MHz and 4-Mbit DRAM
requiring a refresh interval of 1024 cycles every 16 ms, the
refresh divisor would be calculated as follows:
Refresh divisor = refresh period * prescaled clock
= (16x10
-3
sec/1024 cycles) * (66 x 10
6
/16)
= 64.5 (decimal)
= 42h (hexadecimal)
Page Mode DRAM
The AMD-640 system controller generates DRAM addresses
based on the processor address and type of DRAM. Row and
column addresses are multiplexed on the same MA bus. For
non-page mode operations and page misses, the AMD-640
system controller sequentially generates a row address and
column address. On page hits, only a column address is
generated during the DRAM access.
DRAM cycles normally operate in page mode. In this mode,
RAS# is held active after a DRAM access has finished in
anticipation of the next access. RAS# is brought high to
precharge the DRAM only when a subsequent cycle to the
same bank accesses a different DRAM page or an
asynchronous event such as a RAS# time-out occurs.
With Fast Page Mode DRAMs, the column address is latched
on the falling edge of CAS#. FPM DRAMs require CAS# to stay
active throughout the entire cycle, because their drives turn
off when CAS# goes high. While a page cycle continues within
a row, RAS# remains active while CAS# is toggled as the
address (column) changes. Fast Page Mode DRAMs are
enabled or disabled for each bank pair in offset 60h (page
7-24).
DRAM cycles for all processor accesses are generated
synchronously with the CPU clock (HCLK). Critical DRAM
timing parameters including RAS# precharge time and pulse
width, CAS# and write pulse widths, and column address-to-
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