參數(shù)資料
型號： AMD-640
廠商： Advanced Micro Devices, Inc.
英文描述： 64-Bit Socket 7 Interface, Integrated Write back Cache Controller, System Memory Controller, and PCI Bus Controller.(64位系統(tǒng)控制器(包括高速緩沖存儲器控制器，系統(tǒng)存儲器控制器和PCI總線控制器))
中文描述： 64位Socket 7的接口，集成寫回高速緩沖存儲器控制器，系統(tǒng)內(nèi)存控制器和PCI總線控制器。（64位系統(tǒng)控制器（包括高速緩沖存儲器控制器，系統(tǒng)存儲器控制器和的PCI總線控制器））
文件頁數(shù)： 73/159頁
文件大?。?/td> 1900K
代理商： AMD-640
5-34
Functional Operation
AMD-640 System Controller Data Sheet
21090C/0—June 1997
Preliminary Information
Writes To PCI
When the processor writes to the PCI bus, the AMD-640 system
controller acts as a PCI initiator. Figure 5-18 depicts a write to
PCI initiated by the AMD-640 system controller. The controller
drives FRAME#, AD[31:0], and BE[3:0]# to initiate the write
transaction during the first PCLK. FRAME# remains asserted
until the data phase for the last transaction begins or the cycle
is preempted. (Figure 5-18 depicts a single transfer write, so
FRAME# is only asserted for one PCLK.) AD[31:0] contains the
address for the target of the write and BE[3:0]# contain the bus
command (transaction type) information. During the second
PCLK, the AMD-640 system controller begins driving the data
for the write on AD[31:0] and the corresponding byte enables
on BE[3:0]#. There is no need for a turnaround phase because
the controller drives AD[31:0] during both the address and
data phases. Also during the second PCLK, the AMD-640
system controller asserts IRDY# to indicate it is driving the
data and is ready to complete the transaction. In this example
the target is able to decode the address and drive DEVSEL# in
the second clock to indicate that its address matches the one
driven for the cycle, and it drives TRDY# to indicate it is ready
to accept data. On the rising edge of the third PCLK, the target
samples IRDY#, TRDY#, and AD[31:0]. Because both IRDY#
and TRDY# are sampled active, the target accepts the data
written on AD[31:0]. This is a zero- wait state write transaction.
In most cases, the target device will require additional time to
decode the address and complete the write. In this case, the
target delays the assertion of DEVSEL#. If the target requires
additional time to accept the data and complete the write, it
delays the assertion of TRDY# as well.
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