參數(shù)資料
型號: AMD-640
廠商: Advanced Micro Devices, Inc.
英文描述: 64-Bit Socket 7 Interface, Integrated Write back Cache Controller, System Memory Controller, and PCI Bus Controller.(64位系統(tǒng)控制器(包括高速緩沖存儲器控制器,系統(tǒng)存儲器控制器和PCI總線控制器))
中文描述: 64位Socket 7的接口,集成寫回高速緩沖存儲器控制器,系統(tǒng)內(nèi)存控制器和PCI總線控制器。(64位系統(tǒng)控制器(包括高速緩沖存儲器控制器,系統(tǒng)存儲器控制器和的PCI總線控制器))
文件頁數(shù): 44/159頁
文件大?。?/td> 1900K
代理商: AMD-640
Functional Operation
5-5
21090C/0—June 1997
AMD-640 System Controller Data Sheet
Preliminary Information
5.1.3
Read-Around-Writes
This feature minimizes processor stalling by interrupting a
write in progress to service a processor read, effectively giving
read priority over write. The DRAM controller finishes writing
the current word, reads the desired data into the CPU read
buffer, then continues the write from the post write buffer. In
the special case of a read to an address contained in the post
write buffer, the read will not proceed until the write has
completed. Read-around-write is enabled by bit 7 of offset 53h.
5.2
Cache Controller
The AMD-640 system controller supports direct-mapped cache
systems with data sizes ranging from 128 Kbytes to 2 Mbytes. It
can accommodate both synchronous and asynchronous data
SRAMs to provide flexibility for system trade-offs between
cost and performance. Either writeback or writethrough cache
schemes are available, and writeback can be implemented
with or without a modify bit. If no modify bit is used in a
writeback scheme, all lines are treated as modified. This
scheme offers a larger cacheable region (compare Table 5-1
and Table 5-2) but does not perform as well as one with a
modify bit.
5.2.1
Cache Organization
The configuration of tag lines TA[9:0] determines the L2 cache
size and address range. Most L2 cache schemes employ 8-bit
tags, in which case only the lower eight tag lines are used. The
size of the cache determines the particular address lines to
which TA[7:0] correspond. Table 5-1 shows some typical 8-bit
tag configurations.
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