- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366557 > AMD-640 (Advanced Micro Devices, Inc.) 64-Bit Socket 7 Interface, Integrated Write back Cache Controller, System Memory Controller, and PCI Bus Controller.(64位系統(tǒng)控制器(包括高速緩沖存儲器控制器，系統(tǒng)存儲器控制器和PCI總線控制器)) PDF資料下載
參數(shù)資料
| 型號： | AMD-640 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 64-Bit Socket 7 Interface, Integrated Write back Cache Controller, System Memory Controller, and PCI Bus Controller.(64位系統(tǒng)控制器(包括高速緩沖存儲器控制器，系統(tǒng)存儲器控制器和PCI總線控制器)) |
| 中文描述： | 64位Socket 7的接口，集成寫回高速緩沖存儲器控制器，系統(tǒng)內(nèi)存控制器和PCI總線控制器。（64位系統(tǒng)控制器（包括高速緩沖存儲器控制器，系統(tǒng)存儲器控制器和的PCI總線控制器）） |
| 文件頁數(shù)： | 70/159頁 |
| 文件大小： | 1900K |
| 代理商： | AMD-640 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁當(dāng)前第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁
Functional Operation
5-31
21090C/0—June 1997
AMD-640 System Controller Data Sheet
Preliminary Information
following clock edge. Data is transferred between the initiator
and target on each clock edge for which both IRDY# and
TRDY# are asserted. Either the initiator or target can insert
wait states by delaying the assertion of IRDY# or TRDY#,
respectively.
5.4.1
PCI-to-CPU (Read) Transactions
The AMD-640 system controller contains an eight-byte read
buffer which assembles two 32-bit PCI read cycles into one 64-
bit quadword for the CPU data bus. The buffers are also used
when any read crosses a 32-bit boundary. Aligned
byte/word/dword processor reads are passed on to the PCI bus
by the AMD-640 system controller as such. The read buffer is
always enabled.
When the processor reads from the PCI bus, the AMD-640
system controller acts as a PCI initiator. The controller
responds to the read with data from one of its internal buffers
or with data obtained by performing a read operation on the
PCI bus. Figure 5-16 depicts a PCI read initiated by the
AMD-640 system controller. On the first PCLK of the read
transaction the controller initiates the address phase by
asserting FRAME#, driving the PCI bus command on BE[3:0]#,
and driving the address on AD[31:0]. (FRAME# remains
asserted until either the data phase for the last transaction
begins or the cycle is preempted. Figure 5-16 depicts a single-
transfer read, so FRAME# is only asserted for one PCLK.) On
the second PCLK, the controller releases AD[31:0] in what is
known as the turnaround phase, in which ownership of
AD[31:0] changes from the initiator to the target device. The
AMD-640 system controller also begins driving the byte
enables on BE[3:0]# during the second PCLK to indicate which
data paths will be used for the transfer, and asserts IRDY# to
indicate it is ready to accept data. During the third PCLK, the
target device asserts DEVSEL# to indicate that its address
matches the one driven for the cycle and that it is ready to
begin returning data. In addition to DEVSEL#, the target
device drives the requested data on AD[31:0] and asserts
TRDY# to indicate the data is available. On the rising edge of
the fourth PCLK, the AMD-640 system controller samples
IRDY#, TRDY#, and AD[31:0]. Since IRDY# and TRDY# are
both sampled active, the system controller accepts the data on
AD[31:0]. The controller either forwards this data on to the
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AMD-645 | Peripheral Bus Controller(外圍總線控制器) |
| AMD-751 | System Bus, System Memory Controller, AGP Controller, and PCI Bus Controller(系統(tǒng)總線、系統(tǒng)存儲器控制器、AGP控制器和PCI總線控制器) |
| AMD-756 | Peripheral Bus Controller(外圍總線控制器) |
| AMD ATHLON | 32-Bit Microprocessor with 3D Multimedia Performance and Digital Video(32位微處理器帶3D多媒體性能和數(shù)字視頻) |
| AMD-K5 | 32-Bit Superior Price/Performance Value Microprocessor(32位高性/價比微處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AMD-640CHIPSET | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| AMD650-N10D-T | 制造商:SMC Corporation of America 功能描述:Micro Mist Separator, 6000 L/min(ANR), 1-in NPT Port, N.O. Auto Drain, 99.9% Effic. |
| AMD-750 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AMD-750? Chipset Overview |
| AMD-751 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AMD-751 - AMD-751 System Controller Revision Guide |
| AMD-751AC | 制造商:Advanced Micro Devices 功能描述:SYSTEM CONTROLLER, 492 Pin, BGA |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。