參數(shù)資料
型號： AMD-640
廠商： Advanced Micro Devices, Inc.
英文描述： 64-Bit Socket 7 Interface, Integrated Write back Cache Controller, System Memory Controller, and PCI Bus Controller.(64位系統(tǒng)控制器(包括高速緩沖存儲器控制器，系統(tǒng)存儲器控制器和PCI總線控制器))
中文描述： 64位Socket 7的接口，集成寫回高速緩沖存儲器控制器，系統(tǒng)內(nèi)存控制器和PCI總線控制器。（64位系統(tǒng)控制器（包括高速緩沖存儲器控制器，系統(tǒng)存儲器控制器和的PCI總線控制器））
文件頁數(shù)： 47/159頁
文件大?。?/td> 1900K
代理商： AMD-640
5-8
Functional Operation
AMD-640 System Controller Data Sheet
21090C/0—June 1997
Preliminary Information
Cache Misses
Table 5-4 shows the action taken on a cache miss cycle. The
action taken during a cache write miss cycle is identical for
most cache schemes, but varies for different schemes on a read
miss cycle. A cache line is allocated on a read miss only, not on
a write miss.
With a writethrough cache, no writeback action is required
because DRAM-cache coherency is always maintained. With a
writeback cache, the existing cache line must be written back
to DRAM if its modify bit is set. If no modify bit is employed,
the line is assumed to be modified and writeback action is
required unless the line is in a write-protected region.
Processor writeback cycles are handled as normal processor
write cycles. On a PCI cycle, the AMD-640 system controller
snoops the processor’s L1 cache. If it contains the desired PCI
data and it has been modified, the cache line must be written
back. Writeback forwarding allows the PCI to read the
modified data before it is written back.
Table 5-3.
Cache Hit Action Taken
Cycle Type
Processor read
Action Taken
1.
2.
1.
2.
3.
4.
1.
Data (all four bytes) are read from cache.
Cache data, tag, and modify bits are unchanged.
Data with active byte enables are written to the cache.
The tag is unchanged.
The modify bit is set (writeback/modify bit scheme only).
The data is also written to DRAM (writethrough scheme only).
The processor is snooped to write back modified internal cache
line.
Data (all four bytes) are read from cache.
Cache data, tag, and modify bits are unchanged.
The processor is snooped to write the back modified internal
cache line.
Data with active byte enables are written to the cache.
The tag is unchanged.
The modify bit is set (writeback/modify bit scheme only).
The data is also written to DRAM (writethrough scheme only).
Processor write
PCI read
2.
3.
1.
PCI write
2.
3.
4.
5.
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