參數(shù)資料
型號(hào)： AMD-640
廠商： Advanced Micro Devices, Inc.
英文描述： 64-Bit Socket 7 Interface, Integrated Write back Cache Controller, System Memory Controller, and PCI Bus Controller.(64位系統(tǒng)控制器(包括高速緩沖存儲(chǔ)器控制器，系統(tǒng)存儲(chǔ)器控制器和PCI總線控制器))
中文描述： 64位Socket 7的接口，集成寫回高速緩沖存儲(chǔ)器控制器，系統(tǒng)內(nèi)存控制器和PCI總線控制器。（64位系統(tǒng)控制器（包括高速緩沖存儲(chǔ)器控制器，系統(tǒng)存儲(chǔ)器控制器和的PCI總線控制器））
文件頁數(shù)： 53/159頁
文件大?。?/td> 1900K
代理商： AMD-640
5-14
Functional Operation
AMD-640 System Controller Data Sheet
21090C/0—June 1997
Preliminary Information
BIOS (C0000h-C7FFFh and E0000h-EFFFFh, respectively) can
be made cacheable and write-protected by programming the
Shadow Ram Control configuration registers.
The KEN# and EADS# signals maintain consistency in the
cacheable region between the L1 and L2 caches. KEN# alerts
the processor if data being read is cacheable. The EADS#
signal, which the AMD-640 system controller uses to snoop the
L1 cache on PCI-DRAM cycles, is only asserted for data in the
cacheable region.
5.2.5
Cache Parameters
Data transactions with the L2 cache SRAM may differ
depending on the type of SRAM selected. This variance
implies that a specific SRAM speed may be required for
different bus speeds. Examples of SRAM used for various bus
speeds are shown in Table 5-6.
5.2.6
Cache Snooping
Snoop Filtering
Snoop filtering increases processor bandwidth by reducing the
number of snoop cycles (also called inquire cycles) on the local
bus. When a PCI cycle causes a snoop, the AMD-640 system
controller retains the number of the cache line. If a subsequent
access addresses the same line, no snoop cycle is generated.
Snoop Ahead Read
This feature prevents stalling a PCI burst transfer to fetch data
from DRAM. In a PCI read cycle, the AMD-640 system
controller snoops the cache and reads data from there rather
than DRAM if it is present. The controller would then
commence a PCI burst cycle. However, if the next data line
were not in the cache, the controller would have to stall the
burst in order to fetch the next line from DRAM. With snoop
Table 5-6.
SRAMs vs. Bus Speeds
Type of SRAM
60 Mhz
6.7 ns
15 ns
66Mhz
5 ns
12 ns
66 MHz
Wait States
0
0
0
Asynchronous
Synchronous
Sync Pipelined Burst
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