參數(shù)資料
型號： AMD-640
廠商： Advanced Micro Devices, Inc.
英文描述： 64-Bit Socket 7 Interface, Integrated Write back Cache Controller, System Memory Controller, and PCI Bus Controller.(64位系統(tǒng)控制器(包括高速緩沖存儲器控制器，系統(tǒng)存儲器控制器和PCI總線控制器))
中文描述： 64位Socket 7的接口，集成寫回高速緩沖存儲器控制器，系統(tǒng)內(nèi)存控制器和PCI總線控制器。（64位系統(tǒng)控制器（包括高速緩沖存儲器控制器，系統(tǒng)存儲器控制器和的PCI總線控制器））
文件頁數(shù)： 30/159頁
文件大?。?/td> 1900K
代理商： AMD-640
Signal Descriptions
4-3
21090C/0—June 1997
AMD-640 System Controller Data Sheet
Preliminary Information
forwards them to the PCI bus or DRAM, depending on the
address range.
During PCI-to-DRAM cycles, the AMD-640 system controller
drives the address bus to snoop the processor’s cache and the
L2 cache.
HD[63:0]
Host Data Bus
HD[63:0] connects to the host processor’s 64-bit data bus. Each
of the eight bytes of data that comprise this bus is qualified by
a corresponding byte enable signal (BE[7:0]#).
Bidirectional
HITM#
Inquire Cycle Hit To Modified Line Input
The AMD-640 system controller samples HITM# to determine
if an L1 cache snoop has found a modified line. A low on
HITM# indicates that a cache line write by the processor is
imminent. HITM# is deasserted after the line is written.
HLOCK#
Host Bus Lock
The host processor asserts HLOCK# to indicate that it requires
exclusive access to the local bus during a sequence of bus
cycles. When the AMD-640 System Controller samples
HLOCK# low, it withholds bus grants to other PCI initiators. If
a grant has already been issued to a PCI initiator, the AMD 640
will not assert BOFF# for L1 snoops. These actions effectively
suspend a PCI-DRAM transfer until HLOCK# is deasserted.
Input
KEN#/INV
Cache Enable/Invalidate
During host processor read cycles, KEN#/INV functions as the
cache enable signal (KEN#), indicating a cacheable address
when low and a non-cacheable address when high. KEN#/INV
is driven off the rising HCLK edge.
Output
During inquire cycles, KEN#/INV functions as the invalidate
signal (INV), which determines whether an addressed cache
line that is found in the host processor’s L1 cache transitions to
the invalid or shared state.
M/IO#
Memory or I/O
The AMD-640 System Controller samples M/IO# during a bus
cycle to determine whether the host processor is addressing
Input
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