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參數(shù)資料
| 型號(hào)： | AMD-640 |
| 廠(chǎng)商： | Advanced Micro Devices, Inc. |
| 英文描述： | 64-Bit Socket 7 Interface, Integrated Write back Cache Controller, System Memory Controller, and PCI Bus Controller.(64位系統(tǒng)控制器(包括高速緩沖存儲(chǔ)器控制器，系統(tǒng)存儲(chǔ)器控制器和PCI總線(xiàn)控制器)) |
| 中文描述： | 64位Socket 7的接口，集成寫(xiě)回高速緩沖存儲(chǔ)器控制器，系統(tǒng)內(nèi)存控制器和PCI總線(xiàn)控制器。（64位系統(tǒng)控制器（包括高速緩沖存儲(chǔ)器控制器，系統(tǒng)存儲(chǔ)器控制器和的PCI總線(xiàn)控制器）） |
| 文件頁(yè)數(shù)： | 60/159頁(yè) |
| 文件大小： | 1900K |
| 代理商： | AMD-640 |
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Functional Operation
5-21
21090C/0—June 1997
AMD-640 System Controller Data Sheet
Preliminary Information
CAS# delay can be individually programmed in configuration
register 64h.
5.3.4
Shadow RAM
The AMD-640 system controller supports shadowing of system,
video, and other BIOS functions to accelerate access. The BIOS
normally resides in Read Only Memory (ROM) to prevent
altering the content of this crucial system code. Because ROM
is substantially slower than RAM, most systems provide for
copying the ROM contents to the upper memory area of RAM
and making that area read only. The portion of RAM
containing the BIOS copy is referred to as Shadow RAM.
The AMD-640 system controller provides three control
registers (offset 61h–63h, starting on page 7-21) to select the
portions of upper memory for shadowing and to control
read/write access to those areas. The granularity is 16 Kbytes
in the address range C0000h–DFFFFh and 64 Kbytes in the
address range E0000h–FFFFFh. Read and write access can be
enabled independently in each region. Further system
performance enhancement can be achieved by programming
address ranges C0000h–C7FFF and E0000h–FFFFFh to be
cacheable and write-protected.
To copy the ROM code into the targeted shadow memory, set
the access control bits for that area to Write Only, then copy
the ROM code (read address) to the shadow memory (write
address) with the source and destination pointed to the same
physical address. After completion of the copy process, adjust
the access control bits to Read Only.
If shadow RAM is not enabled, addresses A0000h–FFFFFh can
be relocated to the top of local DRAM, increasing memory size
by 384 Kbytes. If only the C segment (C0000h–CFFFFh) and/or
the F segments are used for shadowing, memory is increased
by 256 Kbytes. No DRAM can be relocated if either the D or E
segment is used for shadow memory. Addresses A0000h–
BFFFFh can be reserved for the system management memory
map by setting register 63h bit 1 and cannot be relocated
again. In this case, memory increases are reduced to 256
Kbytes (no shadowing) and 128 Kbytes (C and/or F segments
used for shadowing).
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