參數(shù)資料
型號: AMD-640
廠商: Advanced Micro Devices, Inc.
英文描述: 64-Bit Socket 7 Interface, Integrated Write back Cache Controller, System Memory Controller, and PCI Bus Controller.(64位系統(tǒng)控制器(包括高速緩沖存儲器控制器,系統(tǒng)存儲器控制器和PCI總線控制器))
中文描述: 64位Socket 7的接口,集成寫回高速緩沖存儲器控制器,系統(tǒng)內(nèi)存控制器和PCI總線控制器。(64位系統(tǒng)控制器(包括高速緩沖存儲器控制器,系統(tǒng)存儲器控制器和的PCI總線控制器))
文件頁數(shù): 151/159頁
文件大?。?/td> 1900K
代理商: AMD-640
10-2
IBIS Models
AMD-640 System Controller Data Sheet
21090C/0—June 1997
Preliminary Information
10.2
I/O Buffer Model
AMD provides models of the AMD-640 system controller I/O
buffers for system designers to use in board-level simulations.
These I/O buffer models conform to the
I/O Buffer Information
Specification (IBIS), Version 2.1
.
Each I/O model contains voltage versus current (V/I) and
voltage versus time (V/T) data tables to model the of I/O buffer
behavior accurately.
The following list summarizes the properties of each I/O buffer
model:
I
All data tables contain minimum, typical, and maximum
values to allow for worst-case, typical, and best-case
simulations, respectively.
The pullup, pulldown, power clamp, and ground clamp
device V/I tables contain sufficient data points for accurate
representation of the nonlinear nature of the V/I curves. In
addition, the voltage ranges provided in these tables extend
beyond the normal operating range of the AMD-640 system
controller to accommodate simulators that can yield more
accurate results based on this wider range.
Rising and falling ramp rates are specified.
The min/typ/max V
DD3
operating range is specified as
3.135 V, 3.3 V, and 3.465 V, respectively.
V
il
= 0.8 V, V
ih
= 2.0 V, and V
meas
= 1.5 V.
The R/L/C of the package is modeled.
The capacitance of the silicon die is modeled.
The model assumes 0 capacitance, resistance, inductance,
and voltage in the test load.
I
I
I
I
I
I
I
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