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參數(shù)資料
| 型號(hào)： | AMD-640 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 64-Bit Socket 7 Interface, Integrated Write back Cache Controller, System Memory Controller, and PCI Bus Controller.(64位系統(tǒng)控制器(包括高速緩沖存儲(chǔ)器控制器，系統(tǒng)存儲(chǔ)器控制器和PCI總線控制器)) |
| 中文描述： | 64位Socket 7的接口，集成寫(xiě)回高速緩沖存儲(chǔ)器控制器，系統(tǒng)內(nèi)存控制器和PCI總線控制器。（64位系統(tǒng)控制器（包括高速緩沖存儲(chǔ)器控制器，系統(tǒng)存儲(chǔ)器控制器和的PCI總線控制器）） |
| 文件頁(yè)數(shù)： | 75/159頁(yè) |
| 文件大?。?/td> | 1900K |
| 代理商： | AMD-640 |
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5-36
Functional Operation
AMD-640 System Controller Data Sheet
21090C/0—June 1997
Preliminary Information
5.4.3
PCI Arbitration
The AMD-640 system controller contains the arbitration logic
that allocates ownership of the PCI bus among itself, the
AMD-645 peripheral bus controller, and four other PCI
initiators. For added flexibility, the AMD-640 system
controller allows system designers to select several arbitration
mechanisms. Two mechanisms are controlled by bit 7 in offset
75h (see page 7-39). These mechanisms can be disabled and
replaced by four other choices in offset 76h (page 7-40). The
adjustments include setting priority weight of the processor
over other PCI arbiters, selecting REQ# or FRAME# as the
trigger for new arbitration, and selecting the bus timeout
period.
The PCI bus arbiter implements resource locking, which is
selected via configuration register offset 73h, bit 1 (page 7-37).
When there are no requests for the bus, ownership defaults to
the processor via the AMD-640 system controller. “Parking”
the bus in this way is sometimes referred to as CPU-centric
arbitration.
5.4.4
PCI Configuration
The AMD-640 system controller uses PCI configuration
mechanism #1 to select all of the options available for
interaction with the processor, DRAM, L2 cache, and the PCI
bus. This mechanism is defined in the
PCI Local Bus
Specification Revision 2.1
and described on page 7-1. All
configuration functions for the AMD-640 system controller are
performed via two I/O-mapped configuration registers,
IO_CNTRL (I/O address 0CF8h) and IO_DATA (I/O address
0CFCh).
These two registers are used to access all other internal
configuration registers of the AMD-640 system controller. The
AMD-640 system controller decodes accesses to these two I/O
addresses and handles them internally. A read to a non-
existent configuration register returns a value of FFh.
Accesses to all other I/O addresses are forwarded to the PCI
bus as regular I/O cycles.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AMD-645 | Peripheral Bus Controller(外圍總線控制器) |
| AMD-751 | System Bus, System Memory Controller, AGP Controller, and PCI Bus Controller(系統(tǒng)總線、系統(tǒng)存儲(chǔ)器控制器、AGP控制器和PCI總線控制器) |
| AMD-756 | Peripheral Bus Controller(外圍總線控制器) |
| AMD ATHLON | 32-Bit Microprocessor with 3D Multimedia Performance and Digital Video(32位微處理器帶3D多媒體性能和數(shù)字視頻) |
| AMD-K5 | 32-Bit Superior Price/Performance Value Microprocessor(32位高性/價(jià)比微處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AMD-640CHIPSET | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| AMD650-N10D-T | 制造商:SMC Corporation of America 功能描述:Micro Mist Separator, 6000 L/min(ANR), 1-in NPT Port, N.O. Auto Drain, 99.9% Effic. |
| AMD-750 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AMD-750? Chipset Overview |
| AMD-751 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AMD-751 - AMD-751 System Controller Revision Guide |
| AMD-751AC | 制造商:Advanced Micro Devices 功能描述:SYSTEM CONTROLLER, 492 Pin, BGA |
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