參數(shù)資料
型號(hào)： AMD-640
廠商： Advanced Micro Devices, Inc.
英文描述： 64-Bit Socket 7 Interface, Integrated Write back Cache Controller, System Memory Controller, and PCI Bus Controller.(64位系統(tǒng)控制器(包括高速緩沖存儲(chǔ)器控制器，系統(tǒng)存儲(chǔ)器控制器和PCI總線控制器))
中文描述： 64位Socket 7的接口，集成寫回高速緩沖存儲(chǔ)器控制器，系統(tǒng)內(nèi)存控制器和PCI總線控制器。（64位系統(tǒng)控制器（包括高速緩沖存儲(chǔ)器控制器，系統(tǒng)存儲(chǔ)器控制器和的PCI總線控制器））
文件頁數(shù)： 132/159頁
文件大?。?/td> 1900K
代理商： AMD-640
Configuration Registers
7-35
21090C/0—June 1997
AMD-640 System Controller Data Sheet
Preliminary Information
Bit 7
Retry Status (RWC)
—This bit indicates that a CPU-to-PCI transaction has
been retried unsuccessfully either 16 or 64 times (see Bits 5–4). Write a 1
to this bit position to clear the bit.
0=No retry has occurred (default)
1=Retry has occurred
Retry Timeout Action (RW)
0=Retry continuously and record status only (default)
1=Flush buffer and return FFFFFFFFh for read
Retry Count and Retry Backoff (RW)
00 = Retry two times and backoff processor (default)
01 = Retry 16 times and set Retry Status (Bit 7)
10 = Retry 4 times and backoff processor
11 = Retry 64 times and set Retry Status (Bit 7)
Clear Failed Data And Continue Retry (RW)
—The post write buffer stores data
going from the CPU to the PCI bus. If the target is not ready to accept the
data a retry will occur. If the cycle fails to complete after the number of
retry attempts specified in bits 5–4, the data will be discarded (popped) if
bit 3 is set. This makes room in the post write buffer to accept new data
from the processor.
0=Disable (default)
1=Flush (pop) the failed data and continue posting when posting retries
fail
Processor Backoff on PCI Read Retry Failure (RW)
—This feature generates
BOFF# when a PCI read retry fails, momentarily boosting priority of the
PCI.
0=Disabled (default)
1=Enabled
Reduce 1T for FRAME# Generation (RW)
—When this bit is set, FRAME# is
generated one PCI clock earlier than the setting in register 71h, bit 1.
Doing so may cause timing problems and is not recommended.
0=Disabled (default) (recommended)
1=Enabled
Bit 6
Bits 5–4
Bit 3
Bit 2
Bit 1
7.6.3
Processor-to-PCI Flow Control Register #2
(Offset 72h)
Bit 7
6
5
4
3
2
1
Bit 0
Retry Status
0
RTA
0
Retry Count and Backoff
0
CFDCR
0
PBPRRF
0
R1TFG
0
R1TPRPT
0
Reset
0
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參數(shù)描述
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