參數(shù)資料
型號： AMD-640
廠商： Advanced Micro Devices, Inc.
英文描述： 64-Bit Socket 7 Interface, Integrated Write back Cache Controller, System Memory Controller, and PCI Bus Controller.(64位系統(tǒng)控制器(包括高速緩沖存儲器控制器，系統(tǒng)存儲器控制器和PCI總線控制器))
中文描述： 64位Socket 7的接口，集成寫回高速緩沖存儲器控制器，系統(tǒng)內(nèi)存控制器和PCI總線控制器。（64位系統(tǒng)控制器（包括高速緩沖存儲器控制器，系統(tǒng)存儲器控制器和的PCI總線控制器））
文件頁數(shù)： 40/159頁
文件大小： 1900K
代理商： AMD-640
Functional Operation
5-1
21090C/0—June 1997
AMD-640 System Controller Data Sheet
Preliminary Information
5
Functional Operation
5.1
Processor Interface
The AMD-640 system controller responds to CPU-generated
bus signals and activates the PCI, DRAM, and cache state
machines according to the command type and address range.
On memory cycles it drives the processor address onto the
memory bus from its integrated DRAM controller. For PCI
target cycles it drives the PCI bus from its integrated PCI
buffers and control logic.
The AMD-640 system controller maintains coherency of the
processor primary (L1) cache with the rest of the system using
the KEN#, EADS#, and HITM# pins. It monitors the CACHE#
signal from the processor to determine burst cycles and
returns KEN# asserted when data is cacheable. KEN# is
normally active during a memory read cycle unless the
processor address lies outside the cacheable region. In this
case, the AMD-640 system controller deasserts KEN# before
the completion of the first burst transfer so that the data is not
written to the L1 cache. The AMD-640 system controller does
not write data to the secondary (L2) cache when CACHE# is
inactive unless it is programmed to do so by setting bit 2 of
register 52h. It asserts the EADS# signal during DMA and PCI
initiator cycles to snoop the L1 cache. The processor responds
to a cache hit by asserting the HITM# line. This action notifies
the AMD-640 system controller that a modified cache line must
be written back to the system before the intended memory
access can be performed. A snoop filtering mechanism in the
AMD-640 system controller minimizes snoop overhead by
ensuring that consecutive accesses to the same cache line are
snooped only once.
5.1.1
Write Posting
The AMD-640 system controller contains four write buffers to
enhance memory write performance. Each buffer can hold one
entire cache line, also referred to as a data block, which is 32
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