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參數(shù)資料
| 型號： | HMS30C7202N |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Highly-intergrated MPU |
| 中文描述： | 高intergrated微處理器 |
| 文件頁數(shù)： | 91/179頁 |
| 文件大?。?/td> | 2127K |
| 代理商： | HMS30C7202N |
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HMS30C7202N
2004 MagnaChip Semiconductor Ltd. All Rights Reserved. Version 1.1
- 86 -
9.5
This section describes the implementation-specific options of USB protocol for a device controller. It is
assumed that the user has knowledge of the USB standard. This USB Device Controller (USBD) is chapter 9
(of USB specification) compliant, and supports standard device requests issued by the host. The user should
refer to the Universal Serial Bus Specification revision 1.1 for a full understanding of the USB protocol and its
operation. (The USB specification 1.1 can be accessed via the World Wide Web at:
http://www.usb.org
). The
USBD is a universal serial bus device controller (slave, not hub or host controller) which supports three
endpoints and can operate half-duplex at a baud rate of 12 Mbps. Endpoint 0,by default is only used to
communicate control transactions to configure the USBD after it is reset or physically connected to an active
USB host or hub. Endpoint 0's responsibilities include connection, address assignment, endpoint configuration
and bus numeration.
The connected host that can get a device descriptor stored in USBD’s internal ROM via endpoint 0 configures
the USBD. The USBD uses two separate 32 x 8 bit FIFO to buffer receiving and transmitting data to/from the
host. The external pins dedicated to this interface are UVPO, UVP, UVMO, UVM, URCVIN, nUSBOE and
USUSPEND. These signals should be connected to USB transceiver such as PDIUSBP11 provided by Philip
Semiconductor. Refer to data sheet PDIUSBP11). The CPU can access the USBD using Interrupt controller,
by setting the control register appropriately. This section also defines the interface of USBD and CPU.
* Notice: Don’t use this USB device function with a LS device (like a USB mouse) in a same HUB.
FEATURES
z
Full universal serial bus specification 1.1 compliant.
z
Receiver and Transceiver have 32 bytes FIFO individually (this supports maximum data packet
size of bulk transfer).
z
Internal automatic FIFO control logic. (According to FIFO status, the USBD generates Interrupt
service request signals to the CPU)
z
Supports high-speed USB transfer (12Mbps).
z
There are two endpoint of transmitter and receiver respectively, totally three endpoints including
endpoint 0 that has responsibility of the device configuration.
z
CPU can access the internal USB configuration ROM storing the device descriptor for Hand-held
PC (HPC) by setting the predefined control register bit.
z
USB protocol and device enumeration is performed by internal state-machine in the USBD.
z
The USBD only supports bulk transfer of 4-transfer type supported by USB for data transfer.
z
Endpoint FIFO (Tx, Rx) has the control logic preventing FIFO overrun and under run error.
Note
Product ID: 7210 Vendor ID: 05b4 * can be modified
Reference document - Hms30c7210_UsbDownLoad_V1.3.2Guide_with_Errata.pdf
[Location:
http://www.MagnaChip.com
–SP-MCU-ARM Core Based-HMS30C7210 Reference Design Kit-
Miscellany]
USB Slave Interface
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