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參數(shù)資料
| 型號： | HMS30C7202N |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Highly-intergrated MPU |
| 中文描述： | 高intergrated微處理器 |
| 文件頁數(shù)： | 101/179頁 |
| 文件大?。?/td> | 2127K |
| 代理商： | HMS30C7202N |
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HMS30C7202N
2004 MagnaChip Semiconductor Ltd. All Rights Reserved. Version 1.1
- 96 -
10.1.2.1
ADC Control Register (ADCCR)
User can set ADCPD to save power consumption by ADC. But ADC needs 10-40 ms to self calibrate for
normal operation. DIRECTC bit can be used for direct accessing from CPU to ADC without interface function
logic. All direct control signals are describe in ADCDIRCR register field. Basically ADC core converts Analog
data to Digital data continuously in every 16 ADC operation-clocks.
ADC operation clock is “aclk” (3.6864MHz)
called as “PCLK” in SLOW APB
WAIT bit field select conversion time of ADC because in certain case interface logic can read wrong or
unstable value from ADC. SOP bit can be used for one-shot operation to save power. When this bit is set and
all ADC functions are disabled then interface logic strobe “power down” signal to ADC core. LONGCAL signal
selects self-calibration time. Initially this bit set as “0” it means short calibration time (about 10 ms). But if first a
couple of data were wrong value, user should select long calibration time (about 40 ms).
0x8002.9000
7
ADCPD
6
DIRECTC
3
WAIT
2
1
SOP
0
LONGCAL
Bits
7
Type
R/W
Function
ADC power down bit. Write “1” to go ADC power save mode.
This bit blocks the clock to ADC, so ADC consumes no power when this bit is set. But after
release this bit, ADC need 10 ~ 40 ms calibration time to normal operation.
If this bit was set, CPU access directly ADC through DIRCR and directly read ADC result
value through DIRDATA register.
Reserved
Select ADC conversion wait time. It is for capture timing of the data from ADC to internal
register.
00: no wait (read after 16 cycles, default wait time)
01: 2 clock wait (read after 18 cycles)
10: 4 clock wait (read after 20 cycles)
Self Operate Power down bit. When this bit is set, AIOSTOP bit will strobe high when no ADC
functions are enabled.
Long calibration time. The default ADC calibration time is 10 ms but when needed ADC can
be calibrated during 40ms with this bit.
Short calibration time need 96 cycles of 8 kHz OCLK or 128 cycles of 11 kHz OCLK and the
long time need 384 cycles of 8 kHz or 512 cycles of 11 kHz OCLK. OCLK is determined from
SRATE bit of ADCSDCR.
ADCCR.
LONGCAL bit
SRATE bit
(the number of OCLK cycles)
0
0
0
1
1
0
1
1
6
R/W
5:4
3:2
-
R/W
1
R/W
0
R/W
ADCSCR.
Calibration Time
96
128
383
511
10.1.2.2
ADC Touch Panel Control Register (ADCTPCR)
This register control functions related with touch panel interface.
HMS30C7210 supports only external drive
for touch panel, so prudent setting of this register is needed.
0x8002.9004
7
TPEN
6
TINTMSK
5
SWBYPSS
4
SWINVT
3
INTTDEN
2
SSHOT
1
TRATE
0
Bits
7
Type
R/W
Function
Touch panel read enable bit.
Write “1” to enable touch panel function.
Touch panel read interrupt mask bit.
Write “1” to enable touch panel interrupt.
Touch panel drive signal bypass bit for external drive circuit.
You must set this bit
to bypass
switching signals to external pins such as SW_XP, SW_XN, SW_YP and SW_YN.
6
R/W
5
R/W
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