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參數(shù)資料
| 型號： | HMS30C7202N |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Highly-intergrated MPU |
| 中文描述： | 高intergrated微處理器 |
| 文件頁數(shù)： | 46/179頁 |
| 文件大?。?/td> | 2127K |
| 代理商： | HMS30C7202N |
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HMS30C7202N
2004 MagnaChip Semiconductor Ltd. All Rights Reserved. Version 1.1
- 41 -
SDRAM device-dependent.
The settling time is referenced from when the SDRAM CLK starts. The processor should wait for the settling
time before enabling the SDRAM controller refreshes, by setting the R bit in the SDRAM control register. The
SDRAM controller automatically provides an auto refresh cycle for every refresh period programmed into the
Refresh Timer when the R bit is set. The processor must wait for sufficient time to allow the manufacturer's
specified number of auto-refresh cycles before writing to the SDRAM’s mode register.
The SDRAM's mode register is written to via its address pins (A[14:0]). Hence, when the processor
wishes to write to the mode register, it should read from the binary address (AMBA address bits [24:9]),
which gives the binary pattern on A[14:0] which is to be written. The mode register of each of the
SDRAMs may be written to by reading from a 64Mbyte address space from the SDRAM mode register
base address.
The correspondence between the AMBA address bits and the SDRAM address lines (A[14:0])
is given in the Row address mapping of Table 6-2 SDRAM Row/Column Address Map. Bits [25] of the AMBA
address bus select the device to be initialized.
The SDRAM must be initialized to have the same CAS latency as is programmed into C[1:0] bits of the
SDRAM control register, and always to have a burst length of 8.
6.4
SDRAM Memory Map
The SDRAM controller can interface with up to two SDRAMs of 1Mx16, 4Mx16, 8Mx16 or 16Mx16 density.
The SDRAMs may be organized in either two or four banks. The controller can address 64Mbyte, subdivided
into two 32Mbyte blocks, one for each SDRAMs.
The mapping of the AMBA address bus to the SDRAM row and column addresses is given in Table 6-2. The
first row of the diagram indicates the SDRAM Controller Address output (SA[14:0]) and the SDRAM address
bit (BS1, BS0,A12~A0); If you use 64Mbit SDRAM, you should connect A11~A0 to SA[11:0] and BS0~1 to
SA[13:12].
The remaining numbers indicate the AMBA address bits MBA[24:1].
SDRAM
ADDR
A12
BS0
BS1
A11
A10
A9
A8
Row
16Mbit
1
Col
16Mbit
1
Row
64Mbit
Col
64Mbit
Row
128Mbit
Col
128Mbit
Row
256Mbit
Col
256Mbit
Mode
Write
Summary
24
10
9
22
20
21
19/23
Table 6-2 SDRAM Row/Column Address Map
Notes
(1) For the 16Mbit device, SDRAM address line A11 should be connected to the HMS30C7202 pin SA[13](BS0), and the
SDRAM address line A9 should be connected to the HMS30C7202 pin SA[12](BS1). The HMS30C7202 address lines
SA[11] and SA[9] should not be connected.
(2) Since all burst accesses commence on a word boundary, and SDRAM addresses are non-incrementing (the address
incremented is internal to the device), column address zero will always be driven to logic `0'.
* An asterisk denotes the address lines that are used by the SDRAM.
The start address of each SDRAM is fixed to a 32Mbyte boundary. The memory management unit will be used
to map the actual banks that exist into contiguous memory as seen by the ARM. Bits [25] of the AMBA address
SA[14]
SA[13]
SA[12]
SA[11]
SA[10]
SA[9]
SA[8]
SA[7]
A7
18*
SA[6
A6
17*
SA[5]
A5
16*
SA[4
A4
15*
SA[3]
A3
14*
SA[2]
A2
13*
SA[1]
A1
12*
SA[0]
A0
11*
24
10*
9*
22
20*
Note
19*
24
10*
9*
Note1
20
Note
23
8*
7*
6*
5*
4*
3*
2*
Note2
24
10*
9*
22*
20*
21*
19*
18*
17*
16*
15*
14*
13*
12*
11*
24
10*
9*
22
20
21
23
8*
7*
6*
5*
4*
3*
2*
Note2
24
10*
9*
22*
20*
21*
19*
18*
18*
16*
15*
14*
13*
12*
11*
24
10*
9*
22
20
21
23*
8*
7*
6*
5*
4*
3*
2*
Note2
24*
10*
9*
22*
20*
21*
19*
18*
18*
16*
15*
14*
13*
12*
11*
24
10*
9*
22
20
21
23*
8*
7*
6*
5*
4*
3*
2*
Note2
24*
10*
9*
22*
20*
21*
19*
18*
17*
16*
15*
14*
13*
12*
11*
18/8
17/7
16/6
15/5
14/4
13/3
12/2
11*
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