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參數(shù)資料
| 型號(hào)： | HMS30C7202N |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Highly-intergrated MPU |
| 中文描述： | 高intergrated微處理器 |
| 文件頁(yè)數(shù)： | 66/179頁(yè) |
| 文件大?。?/td> | 2127K |
| 代理商： | HMS30C7202N |
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HMS30C7202N
2004 MagnaChip Semiconductor Ltd. All Rights Reserved. Version 1.1
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1 - LcdLP pin is active LOW and inactive HIGH.
Invert Vsync
The Invert VSync (IVS) bit is used to invert the polarity of the LcdFP signal.
0 - LcdFP pin is active HIGH and inactive LOW.
1 - LcdFP pin is active LOW and inactive HIGH.
AC Bias Pin Frequency
The 5-bit AC-bias frequency (ACB) field is used to specify the number of line clock periods to
count between each toggle of the AC-bias pin (LcdAC). This pin is used to periodically invert
the polarity of the power supply to prevent DC charge build-up within the display. The value
programmed is the number of lines between transitions, minus 1.
Note
The ACB bit field had no effect on LcdAC in active mode. The pixel clock transitions
continuously in active mode and the AC Bias line is used as an output enable signal
LCD Clock source selection
0 - DMA bus clock (system bus clock)
1 - Video PLL clock (VCLK; in normal operation)
Pixel Clock Divisor
Used to specify the frequency of the pixel clock based on the LCD clock (LcdCLK) frequency.
Pixel clock frequency can range from LcdCLK/2 to LcdCLK/33, where LcdClk is the clock
selected by LCS.
Pixel Clock Frequency = LcdCLK/(PCD+2).
Note that in the case of the LCD, the pixel clock is not the frequency of some nominal clock
rate that individual pixels are output to the LCD. It is the frequency of the LcdCP signal. In
normal mono mode (4-bit interface), four pixels are output per LcdCP cycle, so the PixelClock
is one quarter the nominal pixel rate. In the case of 8-bit interface mono, PixelClock is one-
eighth the nominal pixel rate, since 8 pixels are output per LcdCP cycle. In the case of color,
PixelClock is 0.375 times the nominal pixel rate, because 22/3 pixels are output per LcdCP
cycle. If the LCD and VGA are operating concurrently, and sharing DMA data, then in color
mode the pixel clock should normally be 3/8 the VGA clock. To achieve this, PCD should be
7programmed to the value 0 and the skip4 bit set to "1". The skip4 bit produces a null clock
cycle (no high phase) every fourth clock cycle.
11
R/W
10:6
R/W
5
R/W
4:0
R/W
8.2.8
LCD Test Register
The LCD test register contains bits that allow certain LCD signals to be output on the LCD pins for test
purposes. This register should not normally be used. The register is reset to all zero, and this will result in
normal operation.
0x80010040
7
6
5
4
3
2
1
8
TCOUNT
0
TEST
MODE
TCC
TLC
TCR
TLR
TCF
TRF
TLDATA
Bits
31:9
8
7
6
5
4
3
2
1
0
Type
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Reserved
Separates the 10-bit counter into nibbles for the test purpose
For production test of grayscaler, never write a "1" to these registers in normal use.
For production test of grayscaler, never write a "1" to these registers in normal use.
For production test of grayscaler, never write a "1" to these registers in normal use.
For production test of grayscaler, never write a "1" to these registers in normal use.
For production test of grayscaler, never write a "1" to these registers in normal use.
For production test of grayscaler, never write a "1" to these registers in normal use.
Walking one's pattern used in place of SDRAM data for the LCD controller
Test mode bit for grey-scaler
8.2.9
Grayscaler Test Registers
The registers GSFrame State, GSRow State and GS Column State are used for the purpose of production test
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