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參數(shù)資料
| 型號(hào)： | HMS30C7202N |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Highly-intergrated MPU |
| 中文描述： | 高intergrated微處理器 |
| 文件頁(yè)數(shù)： | 65/179頁(yè) |
| 文件大?。?/td> | 2127K |
| 代理商： | HMS30C7202N |
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HMS30C7202N
2004 MagnaChip Semiconductor Ltd. All Rights Reserved. Version 1.1
- 60 -
15:10
R/W
Vertical Sync Pulse Width
The 6-bit vertical sync pulse width (VSW) field is used to specify the pulse width of the vertical
synchronization pulse in active mode, or is used to add extra dummy line clock delays
between frames in passive mode. Should be small for passive LCD, but should be long
enough to re-program the video palette under interrupt control, without writing the video
palette at the same time as video is being displayed. The register is programmed with the
number of lines of VSync minus one.
Lines Per Screen
The Lines Per Screen (LPS) bit-field is used to specify the number of lines or rows per LCD
panel being controlled. LPS is a 10-bit value that represents 1-1024 Lines Per Screen. The
register is programmed with the number of lines per screen minus 1.
9:0
R/W
8.2.7
LCD Timing 2 Register
LCD Timing 2 Register (LcdTiming2) controls various functions associated with the timing of the LCD controller.
0x80010028
15
SLV
14
IEO
13
IPC
12
IHS
27
26
25
CPL
9
24
23
22
21
20
19
18
17
16
Skip4
11
IVS
BCD
10
ACB
8
7
6
5
LCS
4
PCD
3
2
1
0
Bits
31:28
27
Type
-
R/W
Function
Reserved
Set this bit to "1" when running a color passive LCD with slave mode. This produces an
irregular clock to the LCD, where every fourth clock pulse is suppressed (the clock stays LOW
for one clock period). This is necessary because two-and-two-third pixels per clock, which are
sent to the LCD, is not an integer multiple. This means that three clocks will be output every
four-clock period. If PCD is zero, then eight pixels will be output every eight LcdClk periods,
since the LCD CP clock will be half the frequency of LcdClk.
Bypass Pixel Clock Divider
Setting this bit allows an undivided LCD clock to be output on LCD. This bit could only be set
for TFT mode but not in normal cases.
Clocks Per Line
This is the actual number of clocks output to the LCD panel each line, minus one. This must
be programmed, in addition to the PPL field in the LCD Timing 0 Register. The number of
clocks per line is the number of pixels per line divided by 1, 4, 8 or two-and-two-thirds for TFT
mode, mono 4-bit mode, mono 8-bit, or color STN mode (22/3) respectively.
Slave mode
Slave (or genlock) LCD to VGA video. The HSync and VSync are locked to the VGA timing
generator. The LCD horizontal timing must be carefully programmed if sharing DMA data
Invert Output Enable
The Invert Output Enable (IEO) bit is used to select the active and inactive state of the output
enable signal in active display mode. In this mode, the AC-bias pin is used as an enable that
signals the off-chip device when data is actively being driven out using the pixel clock. When
IEO=0, the LcdAC pin is active HIGH. When IEO=1, the LcdAC pin is active LOW. In active
display mode, data is driven onto the LCD's data lines on the programmed edge of LcdCP
when LcdAC is in its active state.
0 - LcdAC pin is active HIGH in TFT mode
1 - LcdAC pin is active LOW in TFT mode
Invert Pixel Clock
The Invert Pixel Clock (IPC) bit is used to select which edge of the pixel clock pixel data is
driven out onto the LCD's data lines. When IPC=0, data is driven onto the LCD's data lines on
the rising-edge of LcdCP. When IPC=1, data is driven onto the LCD's data lines on the falling-
edge of LcdCP.
0 - Data is driven on the LCD's data lines on the rising-edge of LcdCP.
1 - Data is driven on the LCD's data lines on the falling-edge of LcdCP.
Invert Hsync
The Invert HSync (IHS) bit is used to invert the polarity of the LcdLP signal.
0 - LcdLP pin is active HIGH and inactive LOW.
26
R/W
25:16
R/W
15
R/W
14
R/W
13
R/W
12
R/W
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