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參數(shù)資料
| 型號： | HMS30C7202N |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Highly-intergrated MPU |
| 中文描述： | 高intergrated微處理器 |
| 文件頁數(shù)： | 144/179頁 |
| 文件大?。?/td> | 2127K |
| 代理商： | HMS30C7202N |
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HMS30C7202N
2004 MagnaChip Semiconductor Ltd. All Rights Reserved. Version 1.1
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to the marking state and receives the next valid start bit.
Note
:
Bits 1--4 are the error conditions that produce a Receiver Line Status interrupt whenever any
of the corresponding conditions are detected and the interrupt is enabled.
This bit is the Framing Error (FE) indicator. Bit 3 indicates that the received character did not
have a valid stop bit. Bit 3 is set to logic 1 whenever the Stop bit following the last data bit or
parity bit is detected as a logic 0 bit (Spacing level). The FE indicator is reset whenever the
CPU reads the contents of the Line Status Register. In the FIFO mode this error is associated
with the particular character in the FIFO it applies to. This error is revealed to the CPU when
its associated character is at the top of the FIFO. The UART will try to re-synchronize after a
framing error. To do this it assumes that the framing error was due to the next start bit, so it
samples this "start" bit twice and then takes in the "data".
This bit is the Parity Error (PE) indicator. Bit 2 indicates that the received data character does
not have the correct even or odd parity, as selected by the even-parity-select bit. The PE bit is
set to logic 1 upon detection of a parity error and is reset to logic 0 whenever the CPU reads
the contents of the Line Status Register. In the FIFO mode, this error is associated with the
particular character in the FIFO it applies to. This error is revealed to the CPU when its
associated character is at the top of the FIFO.
This bit is the Overrun Error (OE) indicator. Bit 1 indicates that data in the Receiver Buffer
Register was not read by the CPU before the next character was transferred into the Receiver
Buffer Register, thereby destroying the previous character. The OE indicator is set to logic 1
upon detection of an overrun condition and reset whenever the CPU reads the contents of the
Line Status Register. If the FIFO mode data continues to fill the FIFO beyond the trigger level,
an overrun error will occur only after the FIFO is full and the next character has been
completely received in the shift register. OE is indicated to the CPU as soon as it happens.
The character in the shift register is overwritten, but it is not transferred to the FIFO.
This bit is the receiver Data Ready (DR) indicator. Bit 0 is set to logic 1 whenever a complete
incoming character has been received and transferred into the Receiver Buffer Register or the
FIFO. Bit 0 is reset to logic 0 by reading all of the data in the Receiver Buffer Register or the
FIFO.
3
R
2
R
1
R
0
R
Some bits in LSR are automatically cleared when CPU reads the LSR register, so interrupt handling routine
should be written that if once reads LSR, then keep the value through entire the routine because second
reading LSR returns just reset value.
10.8.2.7
MSR
This register provides the current state of the control lines from the MODEM (or peripheral device) to the CPU.
In addition to this current-state information, four bits of the MODEM Status Register provide change
information. These bits are set to logic 1 whenever a control input from the MODEM change state. They are
reset to logic 0 whenever the CPU reads the MODEM Status Register.
UxBase+0x18
0
DCTS
7
DCD
6
RI
5
DSR
4
CTS
3
DDCD
2
TERI
1
DDSR
Bits
7
Type
Function
This bit is the complement of the Data Carrier Detect (nUDCD) input. If bit 4 of the MCR is set
to a 1, this bit is equivalent to OUT2 in the MCR.
This bit is the complement of the Ring Indicator (nURING) input. If bit 4 of the MCR is set to a
1, this bit is equivalent to OUT1 in the MCR.
This bit is the complement of the Data Set Ready (nUDSR) input. If bit 4 of the MCR is set to
a 1, this bit is equivalent to DTR in the MCR.
This bit is the complement of the Clear to Send (nUCTS) input. If bit 4 (loop) of the MCR is
set to a 1, this bit is equivalent to RTS in the MCR.
This bit is the Delta Data Carrier Detect (nUDCD) indicator. Bit 3 indicates that the nUDCD
input to the chip has changed state since the last time it was read by the CPU. Note:
Whenever bit 0, 1, 2 or 3 is set to logic 1, a MODEM Status Interrupt is generated.
This bit is the Trailing Edge of Ring Indicator (TERI) detector. Bit 2 indicates that the nURING
input to the chip has changed from a LOW to a HIGH state.
This bit is the Delta Data Set Ready (nUDSR) indicator. Bit 1 indicates that the nUDSR input
6
5
4
3
2
1
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