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參數(shù)資料
| 型號(hào)： | HMS30C7202N |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Highly-intergrated MPU |
| 中文描述： | 高intergrated微處理器 |
| 文件頁(yè)數(shù)： | 155/179頁(yè) |
| 文件大?。?/td> | 2127K |
| 代理商： | HMS30C7202N |
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HMS30C7202N
2004 MagnaChip Semiconductor Ltd. All Rights Reserved. Version 1.1
- 150 -
instruction is active. This instruction should be used to preload the boundary-scan register with known data
prior to selecting the INTEST or EXTEST instructions.
CLAMP (0101)
The CLAMP instruction connects a 1 bit shift register (the BYPASS register) between
TDI
and
TDO
. When the
CLAMP instruction is loaded into the instruction register, the state of all output signals is defined by the values
previously loaded into the boundary-scan register. A guarding pattern should be pre-loaded into the boundary-
scan register using the SAMPLE/PRELOAD instruction prior to selecting the CLAMP instruction. In the
CAPTURE-DR state, a logic 0 is captured by the bypass register. In the SHIFT-DR state, test data is shifted
into the bypass register via
TDI
and out via
TDO
after a delay of one
TCK
cycle. Note that the first bit shifted
out will be a zero. The bypass register is not affected in the UPDATE-DR state.
HIGHZ (0111)
The HIGHZ instruction connects a 1 bit shift register (the BYPASS register) between
TDI
and
TDO
. When the
HIGHZ instruction is loaded into the instruction register, all outputs are placed in an inactive drive state. In the
CAPTURE-DR state, a logic 0 is captured by the bypass register. In the SHIFT-DR state, test data is shifted
into the bypass register via
TDI
and out via
TDO
after a delay of one
TCK
cycle. Note that the first bit shifted
out will be a zero. The bypass register is not affected in the UPDATE-DR state.
CLAMPZ (1001)
The CLAMPZ instruction connects a 1 bit shift register (the BYPASS register) between
TDI
and
TDO
. When
the CLAMPZ instruction is loaded into the instruction register, all outputs are placed in an inactive drive state,
but the data supplied to the disabled output drivers is derived from the boundary-scan cells. The purpose of
this instruction is to ensure, during production testing, that each output driver can be disabled when its data
input is either a 0 or a 1. A guarding pattern (specified for this device at the end of this section) should be pre-
loaded into the boundary-scan register using the SAMPLE/PRELOAD instruction prior to selecting the
CLAMPZ instruction. In the CAPTURE-DR state, a logic 0 is captured by the bypass register. In the SHIFT-DR
state, test data is shifted into the bypass register via
TDI
and out via
TDO
after a delay of one
TCK
cycle.
Note that the first bit shifted out will be a zero. The bypass register is not affected in the UPDATE-DR state.
INTEST (1100)
The BS (boundary-scan) register is placed in test mode by the INTEST instruction. The INTEST instruction
connects the BS register between
TDI
and
TD
O. When the instruction register is loaded with the INTEST
instruction, all the boundary-scan cells are placed in their test mode of operation. In the CAPTURE-DR state,
the complement of the data supplied to the core logic from input boundary-scan cells is captured, while the
true value of the data that is output from the core logic to output boundary- scan cells is captured. Note that
CAPTURE-DR captures the complemented value of the input cells for testability reasons. In the SHIFT-DR
state, the previously captured test data is shifted out of the BS register via the
TDO
pin, whilst new test data is
shifted in via the
TDI
pin to the BS register parallel input latch. In the UPDATE-DR state, the new test data is
transferred into the BS register parallel output latch. Note that this data is applied immediately to the system
logic and system pins. The first INTEST vector should be clocked into the boundary-scan register, using the
SAMPLE/PRELOAD instruction, prior to selecting INTEST to ensure that known data is applied to the system
logic. Single-step operation is possible using the INTEST instruction.
IDCODE (1110)
The IDCODE instruction connects the device identification register (or ID register) between
TDI
and
TD
O. The
ID register is a 32-bit register that allows the manufacturer, part number and version of a component to be
determined through the TAP. The IDCODE returned will be that for the ARM720T core. When the instruction
register is loaded with the IDCODE instruction, all the boundary-scan cells are placed in their normal (system)
mode of operation. In the CAPTURE-DR state, the device identification code (specified at the end of this
section) is captured by the ID register.
In the SHIFT-DR state, the previously captured device identification code is shifted out of the ID register via
the
TDO
pin, whilst data is shifted in via the
TDI
pin into the ID register. In the UPDATE-DR state, the ID
register is unaffected.
BYPASS (1111)
The BYPASS instruction connects a 1 bit shift register (the BYPASS register) between
TDI
and
TD
O. When
the BYPASS instruction is loaded into the instruction register, all the boundary-scan cells are placed in their
normal (system) mode of operation. This instruction has no effect on the system pins. In the CAPTURE-DR
state, a logic 0 is captured by the bypass register. In the SHIFT-DR state, test data is shifted into the bypass
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