參數(shù)資料
型號： HMS30C7202N
廠商： Electronic Theatre Controls, Inc.
英文描述： Highly-intergrated MPU
中文描述： 高intergrated微處理器
文件頁數(shù)： 10/179頁
文件大?。?/td> 2127K
代理商： HMS30C7202N
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HMS30C7202N
2004 MagnaChip Semiconductor Ltd. All Rights Reserved. Version 1.1
- 5 -
10.2.2.25
DDATA.............................................................................................................................................106
10.2.2.26
DDIR................................................................................................................................................106
10.2.2.27
DMASK............................................................................................................................................106
10.2.2.28
DBSTAT...........................................................................................................................................106
10.2.2.29
DEDGE ............................................................................................................................................106
10.2.2.30
DCLK...............................................................................................................................................106
10.2.2.31
DPOL................................................................................................................................................106
10.2.2.32
GPIO PORT D Enable Register........................................................................................................106
10.2.2.33
EDATA.............................................................................................................................................107
10.2.2.34
EDIR.................................................................................................................................................107
10.2.2.35
EMASK............................................................................................................................................107
10.2.2.36
EBSTAT............................................................................................................................................107
10.2.2.37
EEDGE.............................................................................................................................................107
10.2.2.38
ECLK................................................................................................................................................107
10.2.2.39
EPOL................................................................................................................................................107
10.2.2.40
GPIO PORT E Enable Register ........................................................................................................107
10.2.2.41
Tic Test mode Register(TICTMDR).................................................................................................107
10.2.2.42
PORTA Multi-function Select register(AMULSEL).........................................................................108
10.2.2.43
SWAP Pin Configuration Register(SWAP).......................................................................................108
10.2.3
GPIO Interrupt.........................................................................................................................................108
10.2.4
GPIO Rise/Fall Time................................................................................................................................109
10.3
I
NTERRUPT
C
ONTROLLER
................................................................................................................................... 110
10.3.1
Block diagram .......................................................................................................................................... 110
10.3.2
Registers................................................................................................................................................... 110
10.3.2.1
Interrupt Enable Register (IER).........................................................................................................111
10.3.2.2
Interrupt Status Register (ISR).......................................................................................................... 112
10.3.2.3
IRQ Vector Register (IVR)............................................................................................................... 113
10.3.2.4
Source Vector Register (SVR0 to SVR30)........................................................................................ 113
10.3.2.5
Interrupt ID Register (IDR).............................................................................................................. 113
10.3.2.6
Priority Set Register (PSR0 to PSR7)............................................................................................... 113
10.4
M
ATRIX
K
EYBOARD
I
NTERFACE
C
ONTROLLER
................................................................................................... 115
10.4.1
External Signals........................................................................................................................................ 115
10.4.2
Registers................................................................................................................................................... 115
10.4.2.1
Keyboard Configuration Register (KBCR)....................................................................................... 116
10.4.2.2
Keyboard Scanout Register(KBSC) ................................................................................................. 116
10.4.2.3
Keyboard Test Register (KBTR)....................................................................................................... 117
10.4.2.4
Keyboard Value Register (KVR0) .................................................................................................... 117
10.4.2.5
Keyboard Value Register (KVR1) .................................................................................................... 117
10.4.2.6
Keyboard Status Register (KBSR).................................................................................................... 117
10.5
PS/2
I
NTERFACE
C
ONTROLLER
........................................................................................................................... 119
10.5.1
External Signals........................................................................................................................................ 119
10.5.2
Registers................................................................................................................................................... 119
10.5.2.1
PSDATA........................................................................................................................................... 119
10.5.2.2
PSSTAT ............................................................................................................................................120
10.5.2.3
PSCONF...........................................................................................................................................120
10.5.2.4
PSINTR............................................................................................................................................121
10.5.2.5
PSTDLO...........................................................................................................................................121
10.5.2.6
PSTPRI.............................................................................................................................................121
10.5.2.7
PSTXMT..........................................................................................................................................122
10.5.2.8
PSTREC ...........................................................................................................................................122
10.5.2.9
PSPWDN..........................................................................................................................................123
10.5.3
Application Notes .....................................................................................................................................123
10.6
RTC..................................................................................................................................................................124
10.6.1
External Signals........................................................................................................................................125
10.6.2
Functional Description.............................................................................................................................125
10.6.3
Registers...................................................................................................................................................125
10.6.3.1
RTC Data Register (RTCDR)...........................................................................................................125
10.6.3.2
RTC Match Register (RTCMR)........................................................................................................126
10.6.3.3
RTC Status Register (RTCS) ............................................................................................................126
10.6.3.4
RTC Control Register (RTCCR).......................................................................................................126
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