參數(shù)資料
型號(hào)： HMS30C7202N
廠商： Electronic Theatre Controls, Inc.
英文描述： Highly-intergrated MPU
中文描述： 高intergrated微處理器
文件頁(yè)數(shù)： 43/179頁(yè)
文件大小： 2127K
代理商： HMS30C7202N
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HMS30C7202N
2004 MagnaChip Semiconductor Ltd. All Rights Reserved. Version 1.1
- 38 -
Note
The MMU (memory management unit) must be programmed according to the actual memory configuration
(combination of 16/64/128/256 Mbit SDRAMs).
The SDRAM controller allows up to four memory banks to be open simultaneously. The open banks may exist
in different physical SDRAM devices.
6.2
Registers
The SDRAM controller has four registers: the configuration, refresh timer, the Write Buffer Flush timer and wait
driver. The configuration register's main function is to specify the number of SDRAMs connected, and whether
they are 2- or 4-bank devices. The refresh timer gives the number of BCLK ticks that need to be counted in-
between each refresh period. The Write Buffer Flush timer is used to set the number of BCLK ticks since the
last write operation, before the write buffer's contents are transferred to SDRAM. The wait driver is used to set
wait delay for external slow device.
Address
Name
Width
Default
0x8000.0000
SDCON
32
0x00700000
0x8000.0004
SDREF
16
0x0080
0x8000.0008
SDWBF
3
0x1
0x8000.000C
SDWAIT
4
0x1
Table 6-1 SDRAM Controller Register Summary
In addition to the SDRAM control registers, the ARM may access the SDRAM mode registers by writing to a
64MByte address space referenced from the SDRAM mode register base address. Writing to the SDRAM
mode registers is discussed further in 6.3 Power-up Initialization of the SDRAMs.
6.2.1
SDRAM Controller Configuration Register (SDCON)
Description
Configuration register
Refresh timer
Write back buffer flush timer
Wait driver register
0x8000.0000
2
…
B0
-
31
S1
30
S0
…
-
24
W
23
R
22
A
21
C1
20
C0
19
D
18
C
17
B
…
-
7
E1
6
B1
…
-
3
E0
Bits
31:30
Type
R
Function
SDRAM controller Status
11:Reserved 10:Self refresh 01:Busy 00:Idle
Wait driver enable bit for test purpose
Normal SDRAM controller refresh enable
1 = the SDRAM controller provides refresh control
0 = the SDRAM controller does not provide refresh
Auto pre-charge on ASB accesses
1 = auto pre-charge (default)
0 = no auto pre-charge
If auto pre-charge is enabled, SDRAM controller issues "Read/Write with Auto Pre-charge"
command instead of normal "Read/Write" command.
So, SDRAM controller generates "Active" command before each Read/Write operation.
If auto-pre-charge is disabled, SDRAM controller uses normal "Read/Write" command
and SDRAM page that is accessed before remains active.
So, SDRAM Controller automatically issues "Pre-charge" command only in the case that
One SDRAM page is active and there is need to read/write the other page address in the
same bank.
You had better disable auto pre-charge bit, if a number of SDRAM accesses occur in the
same page boundary - You can perform SDRAM "Read/Write" command fastly without
"Pre-charge" & "Active" command.
11:CAS latency3 10:CAS latency2 01:CAS latency1 00:Reserved
SDRAM bus tri-state control
0 = the controller drives the last data onto the SDRAM data bus (default)
1 = the SDRAM bus is tri-stated except during writes
24
23
R/W
R/W
22
R/W
21:20
19
R/W
R/W
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