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參數(shù)資料
| 型號(hào)： | HMS30C7202N |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Highly-intergrated MPU |
| 中文描述： | 高intergrated微處理器 |
| 文件頁數(shù)： | 32/179頁 |
| 文件大?。?/td> | 2127K |
| 代理商： | HMS30C7202N |
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HMS30C7202N
2004 MagnaChip Semiconductor Ltd. All Rights Reserved. Version 1.1
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5
The HMS30C7202 is designed primarily for HPC and other portable computing applications. Therefore there
are 4 operating modes to reduce power consumption and extend battery life.
z
RUN - normal operation (used for CPU-intensive tasks)
z
SLOW - half-speed operation used when the application interacts with a user (e.g. word processing)
z
IDLE - where the CPU operation is halted but peripherals operation continue (such as screen refresh, or serial
communications)
z
SLEEP & DEEP SLEEP - This mode will be perceived as `OFF' by the user, but the SDRAM contents is maintained and
only the real-time clock is running.
The transition between these modes is controlled by the PMU (see also 7.3 Power management states, page
7-5). The PMU is an ASB slave unit to allow the CPU to write to its control registers, and is an ASB master unit
to provide the mechanism for stopping the ARM core's internal clock.
5.1
Block Functions
CLOCK generator
The CLOCK generator module controls the PLLs and gating clocks while the PLL outputs are unknow and to
ensure that clocks are available during test modes and during RESET sequences.
FCLK (ARM Processor and SDRAM controller clock)
Derived from PLL3, programmable between 49.7664 MHz and 82.944 MHz by a 6-bit register (default
frequency is 70.0416 MHz).
There are two methods for updating frequency, depending upon the state of bit 6 of the Clock Control register
ClkCtl (see ClkCtl register on page 7-11). If bit 6 is set, then any data written to bits [5:0] of the ClkCtl register
are immediately transferred to the pins of PLL3, thus causing the loop to unlock and to mute FCLK. This is
only a safe mode of operation if PLL3 frequency and mark-space ratio is guaranteed to be within limits
immediately after the Lock Detect signal has become active. If bit 6 is NOT set, then the HMS30C7202 must
enter DEEP sleep mode before bits [5:0] of the Clock Control register are transferred to PLL3.
To switch between the two frequencies when bit 6 is not set:
z
Software writes the new value into the ClkCtl register
z
Set a Real Time Clock Alarm to wake the HMS30C7202 in 2 seconds
z
Enter DEEP SLEEP Mode by writing to the PMUMode Register
z
The HMS30C7202 will power up with PLL3 running at the new frequency
BCLK
Bus Clock is generated by the PMU by dividing FCLK by 2.
VCLK
VCLK is generated by PLL1 and clocks the LCD controller. The frequency is selectable between 24.8832MHz
or 41.472MHz (default is 30.4128 MHz). The VCLK PLL is disabled when on BnRES is active or when the
PMU is put into DEEP SLEEP mode. On exit from either of these conditions, the VCLK PLL must be re-
enabled by software.
Changing Frequency:
1.
Software must first disable the VCLK pll, by writing a `0' to the PLL1Enable bit of the ClkCtl register.
2.
Write the new value to the PLL1Freq bit.
3.
Re-enable the VCLK pll by writing 1 to the PLL1Enable bit.
CCLK
CCLK is generated by PLL2 and clocks the USB block - Nominally 48MHz. The CCLK PLL is disabled when
BnRES active or when the PMU is put into DEEP SLEEP mode. On exit from either of these conditions, the
CCLK PLL must be re-enabled by software.
PMU state machine
The state machine handles the transition between the power management states described below. The CPU
PMU & PLL
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