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參數(shù)資料
| 型號： | HMS30C7202N |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Highly-intergrated MPU |
| 中文描述： | 高intergrated微處理器 |
| 文件頁數(shù)： | 143/179頁 |
| 文件大小： | 2127K |
| 代理商： | HMS30C7202N |
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HMS30C7202N
2004 MagnaChip Semiconductor Ltd. All Rights Reserved. Version 1.1
- 138 -
UxBase+0x10
0
DTR
7
0
6
0
5
0
4
LOOP
3
-
2
-
1
RTS
Bits
7:5
4
Type
R
Function
These bits are permanently set to logic 0
This bit provides a local loop back feature for diagnostic testing of the UART. When bit 4 is set
to logic 1, the following occur: the transmitter Serial Output (SOUT) is set to the Marking
(logic 1) state; the receiver Serial Input (SIN) is disconnected; the output of the Transmitter
Shift Register is "looped back" into the Receiver Shift Register input; the four MODEM Control
inputs (NCTS, NDSR, NDCD and NRI) are disconnected; and the two MODEM Control
outputs (NDTR and NRTS) are internally connected to the four MODEM Control inputs, and
the MODEM Control output pins are forced to their inactive state (HIGH). On the diagnostic
mode, data that is transmitted is immediately received. This feature allows the processor to
verify the transmit- and received-data paths of the UART.
In the diagnostic mode, the receiver and transmitter interrupts are fully operational. Their
sources are external to the part. The MODEM Control interrupts are also operational, but the
interrupts sources are now the lower four bits of the MODEM Control Register instead of the
four MODEM Control inputs. The interrupts are still controlled by the Interrupt Enable
Register.
Reserved
This bit controls the Request to Send (nURTS) output. Bit 1 affects the NRTS output in a
manner identical to that described above for bit 0.
This bit controls the Data Terminal Ready (nUDTR) output. When bit is set to logic 1, the
NDTR output is forced to logic 0. When bit 0 is reset to logic 0, the NDTR output is forced to
logic 1.
Note
:
The NDTR output of the UART may be applied to an EIA inverting line driver (such as the
DS1488) to obtain the proper polarity input at the succeeding MODEM or data set.
3:2
1
-
0
R/W
10.8.2.6
LSR
This register provides status information to the CPU concerning the data transfer.
UxBase+0x14
0
DR
7
FIFO ERR
6
TEMT
5
THRE
4
BI
3
FE
2
PE
1
OE
Bits
7
Type
R
Function
In the 16C450 mode this is always 0. In the FIFO mode LSR7 is set when there is at least
one parity error, framing error or break indication in the FIFO. LSR7 is cleared when the CPU
reads the LSR, if there are no subsequent errors in the FIFO.
This bit is the Transmitter Empty (TEMT) indicator. Bit 6 is set to a logic 1 whenever the
Transmitter Holding Register (THR) and the Transmitter Shift Register (TSR) are both empty.
It is reset to logic 0 whenever either the THR or TSR contains a data character. In the FIFO
mode this bit is set to one whenever the transmitter FIFO and register are both empty.
This bit is the Transmitter Holding Register Empty (THRE) indicator. Bit 5 indicates that the
UART is ready to accept a new character for transmission. In addition, this bit causes the
UART to issue an interrupt to the CPU when the Transmit Holding Register Empty Interrupt
enable is set HIGH. The THRE bit is set to a logic 1 when a character is transferred from the
Transmitter Holding Register into the Transmitter Shift Register. The bit is reset to logic 0
concurrently with the loading of the Transmitter Holding Register. In the FIFO mode this bit is
set when the XMIT FIFO is empty; it is cleared when at least 1 byte is written to the XMIT
FIFO.
This bit is the Break Interrupt (BI) indicator. Bit 4 is set to logic 1 whenever the received data
input is held in the Spacing (logic 0) state for longer than a full word transmission time (that is,
the total time of Start bit + data bits + Parity + Stop bits). The BI indicator is reset whenever
the CPU reads the contents of the Line Status Register. In the FIFO mode this error is
associated with the particular character in the FIFO it applies to. This error is revealed to the
CPU when its associated character is at the top of the FIFO. When break occurs, only one
zero character is loaded into the FIFO. The next character transfer is enabled after SIN goes
6
R
5
R
4
R
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