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參數(shù)資料
| 型號： | HMS30C7202N |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Highly-intergrated MPU |
| 中文描述： | 高intergrated微處理器 |
| 文件頁數(shù)： | 142/179頁 |
| 文件大?。?/td> | 2127K |
| 代理商： | HMS30C7202N |
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HMS30C7202N
2004 MagnaChip Semiconductor Ltd. All Rights Reserved. Version 1.1
- 137 -
UART. When it is set to logic 1, the serial output (SOUT) is forced to the Spacing (logic 0)
state. The break is disabled by setting logic 0. The Break Control bit acts only on SOUT and
has no effect on the transmitter logic. Note: This feature enables the CPU to alert a terminal in
a computer communications system. If the following sequence is followed, no erroneous or
extraneous characters will be transmitted because of the break.
This bit is the Stick Parity bit. When bits 3, 4 and 5 are logic 1 the Parity bit is transmitted and
checked as logic 0. If bits 3 and 5 are 1 and bit 4 is logic 0 then the Parity bit is transmitted
and checked as logic 1. If bit 5 is a logic 0 Stick Parity is disabled.
This bit is the Even Parity Select bit. When bit 3 is logic 1 and bit 4 is logic 0, an odd number
of logic 1s is transmitted or checked in the data word bits and Parity bit. When bit 3 is logic 1
and bit 4 is logic 1, an even number of logic 1s is transmitted or checked.
This bit is the Parity Enable bit. When bit 3 is logic 1, a Parity bit is generated (transmit data)
or checked (receive data) between the last data word bit and Stop bit of the serial data. (The
Parity bit is used to produce an even or odd number of 1s when the data word bits and the
Parity bit are summed).
This bit specifies the number of Stop bits transmitted and received in each serial character. If
bit 2 is logic 0, one Stop bit is generated in the transmitted data. If bit 2 is logic 1 when a 5-bit
word length is selected via bits 0 and 1, one and a half Stop bits are generated. If bit 2 is a
logic 1 when either a 6-, 7- or 8-bit word length is selected, two Stop bits are generated. The
Receiver checks the first Stop-bit only, regardless of the number of Stop bits selected.
These two bits specify the number of bits in each transmitted and received serial character.
The encoding of bits 0 and 1 is as follows:
Value Character Length
00 5 Bits
01 6 Bits
10 7 Bits
11 8 Bits
5
4
3
2
1:0
R/W
Programmable Baud Generator
The UART contains a programmable Baud Generator that is capable of taking any clock input from DC to
8.0MHz and dividing it by any divisor from 2 to 2
-1. 5.185 MHz(70MHz CPU Clock) is the highest input clock
frequency recommended when the divisor=1. The output frequency of the Baud Generator is 16 x the Baud
[divisor # = (frequency input) / (baud rate x 16)]. Two 8-bit latches store the divisor in a 16-bit binary format.
These Divisor Latches must be loaded during initialization to ensure proper operation of the Baud Generator.
Upon loading either of the Divisor Latches, a 16-bit Baud counter is immediately loaded.
Baud rate table below provides decimal divisors to use with a crystal frequency of 3.6864MHz. For baud rates
of 38400 and below, the error obtained is minimal. The accuracy of the desired baud rate is dependent on the
crystal frequency chosen. Using a divisor of zero is not recommended.
Desired Baud Rate
Decimal Divisor
(Used to generate 16 x Clock)
50
4608
110
2094
300
768
1200
192
2400
96
4800
48
9600
24
19200
12
38400
6
57600
4
115200
2
Table 10-10 Baud Rate with Decimal Divisor at 3.6864MHz Crystal Frequency
10.8.2.5
MCR
This register controls the interface with the MODEM or data set (or a peripheral device emulating a MODEM).
Percent
Between Desired and Actual
-
0.026
-
-
-
-
-
-
-
Error
Difference
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