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參數(shù)資料
| 型號： | HMS30C7202N |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Highly-intergrated MPU |
| 中文描述： | 高intergrated微處理器 |
| 文件頁數(shù)： | 14/179頁 |
| 文件大?。?/td> | 2127K |
| 代理商： | HMS30C7202N |
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HMS30C7202N
2004 MagnaChip Semiconductor Ltd. All Rights Reserved. Version 1.1
- 9 -
1
1.1
The ARM720T core incorporates an 8K unified write-through cache, and an 8 data entry, 4-address entry write
buffer. It also incorporates an MMU with a 64 entry TLB, and WinCE enhancements.
1.2
Video
The integrated LCD controller can control STN displays and TFT displays, up to 640x480 (VGA) resolution
and 16bit color. On mono displays it can directly generate 16 gray scales.
1.3
Memory
HMS30C7202 incorporates two independent memory controllers. A high-speed 16-bit wide interface connects
directly to one or two 16, 64,128 or 256MBit SDRAM devices, supporting DRAM memory sizes in the range 2
to 64MB. A separate 32- bit data path interfaces to ROM or Flash devices. Burst mode ROMs are supported,
for increased performance, allowing operating system code to be executed directly from ROM. Since the ROM
and SDRAM interfaces are independent, the processor core can execute ROM code simultaneously with
video DMA access to the SDRAM, thus increasing total effective memory bandwidth, and hence overall
performance.
1.4
Internal Bus Structure
The HMS30C7202 internal bus organization is based upon the AMBA standard, but with some minor
modifications to the peripheral buses (the APBs). There are three main buses in the HMS30C7202:
1.
The main system bus (the ASB) to which the CPU and memory controllers are connected
2.
The fast APB to which high-bandwidth peripherals are connected
3.
The slow APB (to which timers, the UART and other low-bandwidth peripherals are connected)
There is also a separate video DMA bus.
1.4.1
ASB
ARCHITECTURAL OVERVIEW
Processor
The ASB is designed to allow the ARM continuous access to both, the ROM and the SDRAM interface. The
SDRAM controller straddles both the ASB and the video DMA bus so the LCD can access the SDRAM
controller simultaneously with activity on the ASB. This means that the ARM can read code from ROM, or
access a peripheral, without being interrupted by video DMA.
The HMS30C7202 uses a modified arbiter to control mastership on the main ASB bus. The arbiter only
arbitrates on quad-word boundaries, or when the bus is idle. This is to get the best performance with the
ARM720T, which uses a quad-word cache line, and also to get the best performance from the SDRAM, which
uses a burst size of eight half-words per access. By arbitrating only when the bus is idle or on quad-word
boundaries (A[3:2] = 11), it ensures that cache line fills are not broken up, hence SDRAM bursts are not
broken up.
The SDRAM controller controls video ASB arbitration. This is explained in 6.5 Arbitration on page 39.
1.4.2
Video bus
The video bus connects the LCD controller with the SDRAM controller. Data transfers are DMA controlled. The
video bus consists of an address bus, data bus and control signals to/from the SDRAM controller. The LCD
registers are programmed through the fast APB. The SDRAM controller arbitrates between ASB, VGA access
requests. Video always has higher priority than ASB access requests. The splitting ASB/video bus allows slow
ASB device accesses SDRAM without blocking video DMA.
1.4.3
APB
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