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參數(shù)資料
| 型號： | HMS30C7202N |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Highly-intergrated MPU |
| 中文描述： | 高intergrated微處理器 |
| 文件頁數(shù)： | 145/179頁 |
| 文件大小： | 2127K |
| 代理商： | HMS30C7202N |
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HMS30C7202N
2004 MagnaChip Semiconductor Ltd. All Rights Reserved. Version 1.1
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to the chip has changed state since the last time it was read by the CPU.
This bit is the Delta Clear to Send (nUCTS) indicator. Bit 0 indicates that the nUCTS input to
the chip has changed state since the last time it was read by the CPU.
0
R/W
10.8.2.8
SCR
This 8-bit Read/Write Register does not control the UART in any way. It is intended as a scratchpad register to
be used by the programmer to hold data temporarily.
UxBase+0x1C
0
7
DATA
6
5
4
3
2
1
Bits
7:0
Type
R/W
Function
Temporary data storage
10.8.2.9
UartEn
UxBase+0x30
0
Full Duplex
Force
Uart1 only
SIR Loop
Back
Uart1 only
SIREN
Uart1 only
UARTEN
Bits
7:4
3
Type
-
R/W
Function
Reserved
SIR Loop-back Test (
Uart1 only)
0 = SIR Loop-back Test disable
1 = SIR Loop-back Test enable.
SIR Full-duplex Force (
Uart1 only)
0 = Half Duplex.
1 = Full Duplex.
SIR Enable (
Uart1 only)
0 = SIR Mode disable
1 = SIR Mode enable (
If you use SIR function, you must set this bit with UART En bit at
the same time
).
UART Enable.
0 = UART disable (Power-Down), UART Clock stop.
1 = UART enable.
2
R/W
1
R/W
0
R/W
10.8.3
FIFO Interrupt Mode Operation
When the RCVR FIFO and receiver interrupts are enabled (FCR 0 = 1, IER 0 = 1) RCVR interrupts occur as
follows:
1. The received data available interrupt will be issued to the CPU when the FIFO has reached its
programmed trigger level. It will be cleared as soon as the FIFO drops below its programmed trigger level.
2. The IIR receive data available indication also occurs when the FIFO trigger level is reached, and like the
interrupt, it is cleared when the FIFO drops below the trigger level.
3. The receiver line status interrupt (IIR-06), as before, has higher priority than the received data available
(IIR-04) interrupt.
4. The data ready bit (LSR 0) is set as soon as a character is transferred from the shift register to the RCVR
FIFO. It is reset when the FIFO is empty.
5.
When RCVR FIFO and receiver interrupts are enabled, RCVR FIFO time-out interrupts occurs as follows:
1.
A FIFO time-out interrupt occurs if the following conditions exist: at least one character is in the
FIFO
-
the most recent serial character received was longer than four continuous character times ago
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