參數(shù)資料
型號(hào)： HMS30C7202N
廠商： Electronic Theatre Controls, Inc.
英文描述： Highly-intergrated MPU
中文描述： 高intergrated微處理器
文件頁(yè)數(shù)： 74/179頁(yè)
文件大?。?/td> 2127K
代理商： HMS30C7202N
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HMS30C7202N
2004 MagnaChip Semiconductor Ltd. All Rights Reserved. Version 1.1
- 69 -
9.2
The SPI is a high-speed synchronous serial port. This chapter describes the SPI communication with a MMC
device.
The communication between CP (master) and MMC is controlled by the CP. The data transmission starts
when the CS (chip-select) goes LOW and ends when the CS goes HIGH.
SPI-MMC messages are built from command, response and data-block tokens. Every command, response
and data block is built with one byte (8-bit). Generally every MMC token transferred on the data signal is
protected by CRC bits. But MMC offers also a non-protected mode that allows a system, built with reliable
data links to exclude the hardware or firmware required for CRC generation and verification.
In the non-protected mode, the CRC bits of the command, response and data tokens are still required in the
tokens; they are, however, defined as "don't care" for the transmitters and are ignored by the receivers.
MMC is initialized in the non-protected mode. The CP can turn this option on and off using the CRCONOFF
command (CMD39). We assume that CRC is processed by software.
9.2.1
External Signals
MMC/ SPI Controller
Pin Name
SSDO
SSDI
SSCLK
nSSCS
Type
O
I
O
O
Description
MMC card controller data output
MMC card controller data input
MMC card controller clock output
MMC card controller chip select
9.2.2
Registers (SPI Mode)
Address
0x8001.5000
0x8001.5004
0x8001.5008
0x8001.500C
0x8001.5010
0x8001.5014
0x8001.5018
0x8001.501C
0x8001.5024
Table 9-3 SPIMMC Controller Register Summary
9.2.2.1
SPIMMC Control Register (SPICR)
Name
SPICR
SPISR
XCHCNT
TXBUFF
RXBUFF
TestReg1
TestReg2
ResetReg
TicReg
Width
Default
0x20
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Description
SPI control register
SPI status register
Number of exchange data
TX data buffer (8*8 bits)
RX data buffer (8*8 bits)
Test register 1
Test register 2
SPI reset register
Tic register
0x8001.5000
6
DataRate
5
CS
4
XCHMode
3
TestMode
2
LOOP
1
SPIEN
0
XCH
Bits
7
6
Type
-
R/W
Function
Reserved
This bit sets the baud rate (SPICLK)
0 : SPICLK=BCLK/2
1 : SPICLK=BCLK/4
This bit is the Chip select signal. To communicate with external devices (MMC), CP asserts 0
in this bit.
0 = CP can exchange data with external device (MMC)
1 = CP cannot exchange data with external device (MMC)
This bit determines the direction of transfer
0 = CP have valid data to send to MMC (send mode)
1 = CP have valid data to receive from MMC (receive mode)
0 = Normal operation
1 = the SPI-MMC block is in TIC mode.
In this mode the Clock source is not BCLK/2 but TCLK that is made in the block.
5
R/W
4
R/W
3
R/W
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