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參數(shù)資料
| 型號： | HMS30C7202N |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Highly-intergrated MPU |
| 中文描述： | 高intergrated微處理器 |
| 文件頁數(shù)： | 79/179頁 |
| 文件大?。?/td> | 2127K |
| 代理商： | HMS30C7202N |
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HMS30C7202N
2004 MagnaChip Semiconductor Ltd. All Rights Reserved. Version 1.1
- 74 -
4 for 1.5625MHz (1/32 BCLK)
5 for 0.78125MHz (1/64 BCLK)
6 for 0.390625MHz (1/128 BCLK)
7 for 0.1953125MHz (1/256 BCLK)
DMA Enable.
Reserved
MMC Enable.
2
1
0
R/W
-
R/W
Table 9-5 MMC Mode Register
MMC Controller can be reset by the two methods. First is the system reset. In this case, most registers are
initialized to the default value. But two registers (response FIFO and data FIFO) are not initialized. Second is
the software reset. It is accomplished by writing the 7th bit of MMC mode control register with 1. Its effect is
same with the first. Following table shows the MMC mode control register.
This controller sends the DMA request signal in two cases (Rx & Tx). And if you want to use DMA, you must
set the DmaEn bit of MMC Mode register. For Rx, when the number of data in the FIFO is more then zero, it
generates the request signal. For Tx, when the number of data in the FIFO are less then eight, it generate the
request signal.
Operation frequency can be controlled by setting the ClkRate bit of MMC Mode register. Divisor controls the
rate of MMC clock (MMCCLK). Assume that BCLK has 50MHz frequency.
9.2.6.2
MMC Operation Register
0x8001.5044
0
StartEn
8
7
6
5
4:3
2
1
BusyCheck
StreamEn
WriteEn
DataEn
RespFormat
Initialization
ClkEn
Bits
8
7
6
5
4:3
Type
R/W
R/W
R/W
R/W
R/W
Function
Current command needs the busy check after command operation.
Define stream mode( 1 = stream mode, 0 = block mode )
1 = write, 0 = read. default is read
Indicate that current command contains the data operation
Response format (No response, R1, R2, and R3)
0 for No response
1 for format R1
2 for format R2
3 for format R3
Add the 128 clocks before sending the command
Enable the clock
Start the mmc operation
Table 9-6 MMC Operation Register
All Multimedia Cards require at least 74 clock cycles prior to starting bus communication. and the clock
frequency must be less then the Open-Drain frequency(F_od=0.5Mhz). Therefore the host controller must do
these during power-on.
For generating 74 clock cycles, set initialization bit of MMC Operation register. If initialization bit is set, then
the controller will send additional 128 clocks before send start bit. Although this bit is zero, the controller sends
16 clocks before the start bit for safe operation. And add 8 clocks after the stop bit.
MMC has the four types of the response (No response, R1, R2, and R3). And each format is similar to the
command format. But you need not know what they shape. You just only need to know the length of response
to be stored after the response end. R1 and R3 have one word. And R2 has four words. Its contents are
different according to the each command. You must analysis this content according to the each command
after operation. And the response format can be specified by the RespFormat bits of the operation control
register.
9.2.6.3
MMC Status Register
2
1
0
R/W
R/W
R/W/C
0x8001.5048
8
14
13
12
11
10
9
Detected_n
6
DetIntr
5
ReadyTimeout
4
RespCrcErr
3
DataCrcErr
2
RespTimeout
1
DataTimeout
0
7
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