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參數(shù)資料
| 型號： | HMS30C7202N |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Highly-intergrated MPU |
| 中文描述： | 高intergrated微處理器 |
| 文件頁數(shù)： | 42/179頁 |
| 文件大?。?/td> | 2127K |
| 代理商： | HMS30C7202N |
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HMS30C7202N
2004 MagnaChip Semiconductor Ltd. All Rights Reserved. Version 1.1
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6
SDRAM CONTROLLER
The SDRAM controller operates at the full CPU core frequency (FCLK = SCLK) and is connected to the core
via the ASB bus. Internally the SDRAM controller arbitrates between access requests from the main AMBA
bus, and the video bus.
It can control up to two SDRAMs of 16Mx16 density maximum. To reduce the system power consumption it
can power down these individually using the Clock Enable (CKE). When the MCU is in standby mode the
SDRAMs are powered down into self-refresh mode.
SDRAMs achieve the highest throughput when accessed sequentially – like video data. However accesses
from the core are less regular. The SDRAM controller uses access predictability to maximize the memory
interface bandwidth by having access to the LCD address buses.
Video accesses to the SDRAM occur in fixed-burst lengths of 16 words;
At each Video access, SDRAM
controller issues 4 consecutive "Read" commands of which burst length is 8 half-word. So, If you want to get
the successive 16 words, the start address of SDRAM read must be arranged to 4-Word(8-HalfWord)
boundary - The start address of SDRAM must be 0xXXXX_XXX0.
ARM and DMA controller accesses occur in a fixed-burst length of four words. If the requested accesses are
shorter than four words, then the extra data is ignored. In Addition, ARM/DMA Access SDRAM Controller
discards the data of which the address is not sequentially increased.
For example, If ARM do the 4-
Word "ldm(load Block data)" of which start address is 0x4000_0004, the Address output from SDRAM
Controller to SDRAM is start from 2 (just 4bits from LBS). SDRAM do the 8-HalfWord Burst Read and it's
address sequence is 2-3-4-5-6-7-0-1. In that case, SDRAM Controller discards data from address 0,1 and jost
get the 6-HalfWard Data(Address from 2 to 7). After that, SDRAM Controller issue the "Read" Command again
of which Start address to SDRAM is 8 and gets the 2-HalfWord data(data from SDRAM address 8,9).
FEATURES
z
16 Bits wide external bus interface (two access requires for each word)
z
Supports 16/64/128/256Mbit device
z
Supports 2~64 Mbytes in up to two devices (the size of each memory device may be different)
z
Programmable CAS latency
z
Supports 2/4 banks with page lengths of 256 or 512 half words
z
Programmable Auto Refresh Timer
z
Support low power mode when IDLE (each device’s CKE is disable individually).
z
Support External Device interface with DMA channel 2.
6.1
Supported Memory Devices
2-64Mbytes of SDRAM are supported with any combination of one or two 16/64/128/256Mbit devices. Each
device is mapped to a 32 Mbyte address space. The MMU (memory management unit) maps different device
combinations (e.g. 16- and 64Mbit devices) into a continuous address space for the ARM core. Note that
16Mbit devices appear eight times, and 64Mbit devices appear twice in the memory map.
Total Memory
16Mbit devices
64Mbit devices
2Mbyte
1
-
4Mbyte
2
-
8Mbyte
-
1
16Mbyte
-
2
32Mbyte
-
-
64Mbyte
-
-
128Mbit devices
-
-
-
1
2
-
256Mbit devices
-
-
-
-
1
2
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