參數(shù)資料
型號： HMS30C7202N
廠商： Electronic Theatre Controls, Inc.
英文描述： Highly-intergrated MPU
中文描述： 高intergrated微處理器
文件頁數(shù)： 13/179頁
文件大?。?/td> 2127K
代理商： HMS30C7202N
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HMS30C7202N
2004 MagnaChip Semiconductor Ltd. All Rights Reserved. Version 1.1
- 8 -
LIST OF FIGURES
Figure 5-1 PMU Power Management State Diagram........................................................................ 28
Figure 5-2 PMU Cold Reset Event ................................................................................................... 34
Figure 5-3 PMU Software Generated Warm Reset........................................................................... 35
Figure 5-4 PMU An Externally Generated Warm Reset.................................................................... 36
Figure 6-1 SDRAM Controller Software Example and Memory Operation Diagram......................... 39
Figure 8-1 Video System Block Diagram.......................................................................................... 52
Figure 8-2 5:6:5 Combination of 16bpp Data.................................................................................... 53
Figure 8-3 Palette RAM Entries for 5:6:5 Combination..................................................................... 54
Figure 8-4 Sample Code for 5:6:5 Palette Generation...................................................................... 54
Figure 8-5 LCD Palette Word Bit Field for STN mode ...................................................................... 62
Figure 8-6 LCD Palette Word Bit Field for TFT mode....................................................................... 62
Figure 8-7 Example Mono STN LCD Panel Signal Waveforms........................................................ 63
Figure 8-8 Example TFT Signal Waveforms, Start of Frame ............................................................ 63
Figure 8-9 Example TFT Signal Waveforms, End of Last Line ......................................................... 63
Figure 9-1 USB Block Diagram......................................................................................................... 87
Figure 9-2 USB Serial Interface Engine............................................................................................ 88
Figure 9-3 USB Device Interface Device Controller.......................................................................... 89
Figure 10-3 Interrupt controller block diagram.................................................................................110
Figure 10-4 A flow chart of the keyboard controller..........................................................................115
Figure 10-5 PS/2 Controller Transmitting Data Timing Diagram......................................................121
Figure 10-6 PS/2 Controller Receiving Data Timing Diagram..........................................................122
Figure 10-7 RTC Connection...........................................................................................................124
Figure 10-8 RTC Block Diagram......................................................................................................125
Figure 10-9 WDT Operation in the Watchdog Timer mode..............................................................142
Figure 10-10 WDT Operation in the Interval Timer mode................................................................143
Figure 10-11 Interrupt Clear in the interval timer mode....................................................................145
Figure 10-12 Interrupt Clear in the watchdog timer mode with reset disable...................................146
Figure 10-13 Interrupt Clear in the watchdog timer mode with manual reset...................................146
LIST OF TABLES
Table 2-1 Pin Signal Type Definition.................................................................................................. 17
Table 2-2 External Signal Functions .................................................................................................. 19
Table 4-1 Top-level address map....................................................................................................... 25
Table 4-2 Peripherals Base Addresses.............................................................................................. 26
Table 5-1 PMU Register Summary .................................................................................................... 30
Table 5-2 PMU Bit Settings for a cold Reset Event within PMUSTAT Register.................................. 35
Table 5-3 PMU Bit Settings for a Software Generated Warm Reset within PMUSTAT Register........ 35
Table 5-4 PMU Bit Settings for a Warm Reset within PMUSTAT Register......................................... 36
Table 6-1 SDRAM Controller Register Summary............................................................................... 38
Table 6-2 SDRAM Row/Column Address Map................................................................................... 41
Table 6-3 SDRAM Device Selection .................................................................................................. 42
Table 7-1 Static Memory Controller Register Summary..................................................................... 46
Table 8-1 LCD Colorgrayscale intensities and modulation rates........................................................ 55
Table 8-2 How to order the bit on LD[7:0] in 8-bit color STN mode.................................................... 56
Table 8-3 LCD Controller Register Summary..................................................................................... 56
Table 9-1 DMA Controller Register Summary.................................................................................... 65
Table 10-1 ADC Controller Register Summary .................................................................................. 95
Table 10-2 Interrupt controller Configuration.....................................................................................110
Table 10-3 Interrupt controller Register Summary ............................................................................111
Table 10-4 Matrix Keyboard Interface Controller Register Summary................................................116
Table 10-5 PS/2 Controller Register Summary.................................................................................119
Table 10-6 Non-AMBA Signals within RTC Core Block.....................................................................124
Table 10-7 RTC Register Summary..................................................................................................125
Table 10-8 Timer Register Summary ................................................................................................127
Table 10-9 UART/SIR Register Summary.........................................................................................134
Table 10-10 Baud Rate with Decimal Divisor at 3.6864MHz Crystal Frequency...............................137
Table 10-11 Watchdog Timer Register Summary..............................................................................143
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