- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370643 > HMS30C7202N (Electronic Theatre Controls, Inc.) Highly-intergrated MPU PDF資料下載
參數(shù)資料
| 型號： | HMS30C7202N |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Highly-intergrated MPU |
| 中文描述： | 高intergrated微處理器 |
| 文件頁數(shù)： | 47/179頁 |
| 文件大?。?/td> | 2127K |
| 代理商： | HMS30C7202N |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁當前第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁
HMS30C7202N
2004 MagnaChip Semiconductor Ltd. All Rights Reserved. Version 1.1
- 42 -
bus select the device to be initialized, as described in Table 6-3.
A25
Device selected
0
Device 0
1
Device 1
Table 6-3 SDRAM Device Selection
6.5
AMBA Accesses and Arbitration
The SDRAM controller bridges both the AMBA Main and Video buses. On the Main bus, the SDRAM appears
as a normal slave device. On the Video DMA bus, the SDRAM controller integrates the functions of the bus
arbiter and address decoder. Writes from the main bus may be merged in the quad word merging write buffer.
A Main/Video arbiter according to the following sequence arbitrates access requests from either the Main or
Video buses:
Highest Priority: LCD
Refresh request
Lowest Priority: Main bus peripheral (PMU, ARM, DMA)--order determined by Main bus arbiter.
Video SDRAM accesses always occur in bursts of 16 words. Once a burst has started, the SDRAM controller
provides data without wait states. Video data is only read from SDRAM, no write path is supported.
If a refresh cycle is requested, then it will have lower priority than the Video bus, but will be higher than any
other accesses from the Main bus. Assuming a worst-case BCLK frequency of 8MHz, the maximum, worst-
case latency that the arbitration scheme enforces is 11.5us before a refresh cycle can take place. This is
comfortably within the 16us limit. Note that the 2 external SDRAM devices are refreshed on 2 consecutive
clock cycles to reduce the peak current demand on the power source.
The arbitration of the Main bus is left to the Main bus arbiter. Data transfers requested from the Main bus
always occur as a burst of eight half-word accesses to SDRAM. The Main bus arbiter cannot break into
access requests from the Main bus. In the case where fewer than four words are actually requested by the
Main bus peripheral, the excess data from the SDRAM is ignored by the SDRAM controller in the case of read
operations, or masked in the case of writes. In the case where more than four words are actually requested by
the Main bus peripheral, the SDRAM controller asserts BLAST to force the ASB decoder to break the burst.
In the case of word/half-word/byte misalignment to a quad word boundary (when any of address bits [3:0] are
non-zero at the start of the transfer), BLAST is asserted at the next quad word boundary (bits 3, 2, 1 and 0
properly set 1 for each type) to force the ASB decoder to break the burst.
Sequential half word (or byte) reads are supported and the controller asserting BLAST at quad word boundary.
In the case of byte or half word reads, data is replicated across the whole of the ASB data bus.
Data bus for word access:
31 23 15 7 0
d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
Data bus for half word access:
31 23 15 7 0
d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
Data bus for byte access:
31 23 15 7 0
d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0
6.6
Merging Write Buffer
An eight word merging Write-Buffer is implemented in the SDRAM controller to improve write performance.
The write buffer can be disabled, but its operation is completely transparent to the programmer. The eight
words of the buffer are split into two quad words, the same size as all data transactions to the SDRAMs. The
split into two quad words allows one quad word to be written to at the same time as the contents of the other
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HMS81C2012A | CMOS Single-Chip 8-Bit Microcontroller with A/D Converter & VFD Driver |
| HMS81C2012AK | CMOS Single-Chip 8-Bit Microcontroller with A/D Converter & VFD Driver |
| HMS81C2012ALQ | CMOS Single-Chip 8-Bit Microcontroller with A/D Converter & VFD Driver |
| HMS81C2012AQ | INDUCTOR*100UH*0.73AMP*0.672OHM*15%*SURFACE MOUNT |
| HMS81C2020A | INDCTR, PWR, SMT 1.5UH, 15%, 6.9 A |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HMS30C7210 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ARM Based 32-Bit Microprocessor |
| HMS3224M3 | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:SRAM MODULE 768KBit (32K x 24-Bit) |
| HMS3224M3-10 | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:SRAM MODULE 768KBit (32K x 24-Bit) |
| HMS3224M3-12 | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:SRAM MODULE 768KBit (32K x 24-Bit) |
| HMS3224M3-15 | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:SRAM MODULE 768KBit (32K x 24-Bit) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。