參數(shù)資料
型號(hào)： HMS30C7202N
廠商： Electronic Theatre Controls, Inc.
英文描述： Highly-intergrated MPU
中文描述： 高intergrated微處理器
文件頁(yè)數(shù)： 36/179頁(yè)
文件大?。?/td> 2127K
代理商： HMS30C7202N
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HMS30C7202N
2004 MagnaChip Semiconductor Ltd. All Rights Reserved. Version 1.1
- 31 -
read each time the ARM exits reset mode, so that the ARM can identify what event has caused it to exit from
reset mode.
0x80001020
16
WARM
RESET
8
WARM RST
STATUS
0
POR
STATUS
15
HOTSYNC
INTR
7
ADAPTOR
STATUS
14
ADAPTOR
INTR
6
RTC
STATUS
13
12
MRING
INTR
4
WAKEUP
STATUS
11
WAKEUP
INTR
3
PLL3
LOCK
10
HOTSYNC
STATUS
2
PLL2
LOCK
9
RTC INTR
WDT RST
5
MRING
STATUS
1
PLL1
LOCK
Bits
31:17
16
15
Type
-
W
R/W
Function
Reserved
Warm RESET. Writing a `1' causes nRESET to be asserted. Writing `0' has no effect.
HOTSYNC interrupt Mask. When reads,
0 = Disable Hotsync interrupt from External pin.
1 = Enable Hotsync interrupt from External pin.
No External Power Interrupt Mask. When reads,
0 = Disable PMU interrupt from PMADAPOK LOW.
1 = Enable PMU interrupt from PMADAPOK LOW.
RTCEvt Interrupt Mask. When reads,
0 = Disable PMU interrupt from RTC
1 = Enable PMU interrupt from RTC
RIEvt Interrupt MASK PMU Interrupt Request / Clear
When reads,
0 = Disable PMU interrupt from MRING
1 = Enable PMU interrupt from MRING
OnEvt Interrupt MASK PMU Interrupt Enable
When reads,
0 = Disable PMU interrupt from nPMWAKEUP
1 = Enable PMU interrupt from nPMWAKEUP
HOTSYNC Event
When reads, 0 = Not Hot Sync state; 1 = Hot Sync status
When writes, HotSync Interrupt Clear. Writing a `1' to this bit clears the event bit
WDTEvt: Watch Dog Reset (Warm reset)
When reads,
0 = No Watch dog Timer event occured
1 = A Watch dog timer event has ocurred since last cleared
When writes, Watch dog Reset Clear. Writing a `1' to this bit clears the event bit
RESETEvt: Warm RESET Event (debounced)
When reads,
0 = No Warm RESET event has occurred
1 = A Warm RESET event has occurred since last cleared
When writes, Warm Reset Clear. Writing a `1' to this bit clears the event bit.
PowerFailEvt: ADPATOR NOT OK (debounced)
When reads,
0 = No Power Fail event since last cleared
1 = A Power Fail event has occurred since last cleared
When writes, Power Fail Interrupt Clear. Writing a `1' to this bit clears a pending interrupt bit.
RTCEvt
When reads,
0 = No Real Time Clock (RTC) calendar wake-up event since last cleared
1 = Real Time Clock (RTC) calendar wake-up event since last cleared
When writes, RTC Interrupt Clear. Writing a `1' to this bit clears a pending interrupt bit.
RIEvt (debounced)
When reads,
0 = No Modem Ring Indicate wake-up event since last cleared
1 = Modem Ring Indicate wake-up event since last cleared
When writes, RI Interrupt Clear. Writing a `1' to this bit clears a pending interrupt bit.
14
R/W
13
R/W
12
R/W
11
R/W
When writes to these bits, PMU
Interrupts will be enabling. `1' enables
interrupts to the CPU, `0' masks such
activity. Should the enable bit be set
to one when one of the debounced
event signals is set, then an interrupt
WILL be generated (i.e. the interrupt
is level sensitive, not edge sensitive).
10
R/w
9
R/w
8
R/w
7
R/w
6
R/w
5
R/w
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