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參數(shù)資料
| 型號： | HMS30C7202N |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Highly-intergrated MPU |
| 中文描述： | 高intergrated微處理器 |
| 文件頁數(shù)： | 44/179頁 |
| 文件大?。?/td> | 2127K |
| 代理商： | HMS30C7202N |
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HMS30C7202N
2004 MagnaChip Semiconductor Ltd. All Rights Reserved. Version 1.1
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This bit should be cleared before the IC enters a low power mode. Driving the data lines
avoids floating inputs that could increase device power consumption. During normal
operation the D bit should be set, to avoid data bus drive conflicts with SDRAM.
SDRAM clock enable control
0 = the clock of IDLE devices are disabled to save power (default)
1 = all clock enables are driven HIGH continuously
Write buffer enable
Value = 1 if the write buffer is enabled
Value = 0 if the write buffer is disabled
1 = a device is present at address range 32-64Mbyte
0 = no device present at address range 32-64Mbyte
The bit E is used to control the auto-refresh
Specifies the number of banks of the SDRAM at address range 32-64Mbyte
1 = the SDRAM is a four-bank device
0 = the SDRAM is a two-bank device
1 = a device is present at address range 0-32MByte
0 = no device present at address range 0-32Mbyte
The bit E is used to control the auto-refresh
Specifies the number of banks of the SDRAM at address range 0-32Mbyte
1 = the SDRAM is a four-bank device
0 = the SDRAM is a two-bank device
18
R/W
17
R/W
7
R/W
6
R/W
3
R/W
2
R/W
The SDRAM controller powers-up with E[1:0]=00 and R=0. This indicates that the memory interface is IDLE.
Next, the software should set at least one E bit to 1 with the R bit 0. This will cause both devices to be
precharged (if present). The next operation in the initialization sequence is to auto-refresh the SDRAMs. Note
that the number of refresh operations required is device-dependent. Set R=1 and E[1:0]=00 to start the auto-
refresh process. Software will have to ensure that the prescribed number of refresh cycles is completed before
moving on to the next step. The final step in the sequence is to set R=1 and to set the E bits corresponding to
the populated slots. This will put the SDRAM controller (and the SDRAMs) in their normal operational mode.
After that SDRAM mode register (in the SDRAM, not SDCON) must be initialized as to Write Burst Mode =
"Programmed Burst Length", Burst Type = "Sequential", Burst Length = “8”.
Write
R=0
E[1:0]=00
Write
R=0
E[1:0]=01
Write
R=1
E[1:0]=00
Write
R=1
E[1:0]=According
to slot populated
Refresh complete
Software Example Operation
Memory Operation
No,wait
Yes
IDLE
PRECHARGE
AUTO REFRESH
MEMORY REFRESHING
NORMAL OPERATION
End of Initialization
MEMORY START
Figure 6-1 SDRAM Controller Software Example and Memory Operation Diagram
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