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參數(shù)資料
| 型號(hào)： | HMS30C7202N |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Highly-intergrated MPU |
| 中文描述： | 高intergrated微處理器 |
| 文件頁數(shù)： | 137/179頁 |
| 文件大小： | 2127K |
| 代理商： | HMS30C7202N |
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HMS30C7202N
2004 MagnaChip Semiconductor Ltd. All Rights Reserved. Version 1.1
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10.8
UART/SIR
The 16C550 is a Universal Asynchronous Receiver/Transmitter (UART), with FIFOs, and is functionally
identical to the 16C450 on power-up (CHARACTER mode). The 16550 can be put into an alternate mode
(FIFO mode) to relieve the CPU of excessive software overhead. In this mode internal FIFOs are activated,
allowing 16 bytes plus 3 bit of error data per byte in the RCVR FIFO, to be stored in both receive and transmit
modes. All the logic is on the chip to minimize the system overhead and to maximize efficiency.
The UART performs serial-to-parallel conversion on data characters received from a peripheral device or a
MODEM, and parallel-to-serial conversion on data characters received from the CPU. The CPU can read the
complete status of the UART at any time during the functional operation. Status information reported includes
the type and condition of the transfer operations being performed by the UART, as well as any error conditions
(parity, overrun, framing, or break interrupt).
The UART includes a programmable baud rate generator capable of dividing the timing reference clock input
by divisors of 1 to 2
-1, and producing a 16x clock for driving the internal transmitter logic. Provisions are also
included to use this 16x clock to drive the receiver logic.
The UART has complete MODEM-control capability, and a processor-interrupt system. Interrupts can be
programmed to the user's requirements, minimizing the computing required to handle the communications link.
FEATURES
z
Capable of running all existing 16C450 software.
z
After reset, all registers are identical to the 16C450 register set.
z
The FIFO mode transmitter and receiver are each buffered with 16 byte FIFOs to reduce the
number of interrupts presented to the CPU.
z
Add or delete standard asynchronous communication bits (start, stop and parity) to or from the serial
data.
z
Holding and shift registers in the 16C450 mode eliminate the need for precise synchronization
between the CPU and serial data.
z
Independently controlled transmit, receive, line status and data set interrupts.
z
Programmable baud generator divides any input clock by 1 to 65535 and generates 16x clock
z
Independent receiver clock input.
z
MODEM control functions (CTS, RTS, DSR, DTR, RI and DCD).
z
Fully programmable serial-interface characteristics:
-
5-, 6-, 7- or 8-bit characters
-
Even, odd or no-parity bit generation and detection
-
1-, 1.5- or 2-stop bit generation and detection
-
Baud generation (DC to 230k baud)
z
False start bit detection.
z
Complete status-reporting capabilities.
z
Line breaks generation and detection.
z
Internal diagnostic capabilities:
-
Loopback controls for communications link fault isolation
z
Full prioritized interrupt system controls.
10.8.1
External Signals
Pin Name
nURING
Type
I
Description
UART 0 ring input signal (wake-up signal to PMU).
When LOW, this indicates that the MODEM or data set has received a telephone
ring signal. The nURING signal is a MODEM status input whose condition can be
tested by the CPU reading bit 6 (RI) of the MODEM Status Register. Bit 6 is the
complement of the nURING signal. Bit 2 (TERI) of the MODEM Status Register
indicates whether the nURING input signal has changed from a LOW to a HIGH
state since the previous reading of the MODEM Status Register.
Note
: Whenever the RI bit of the MODEM Status Register changes from a HIGH
to a LOW state, an interrupt is generated if the MODEM Status Interrupt is
enabled. The nURING input from the external PAD is not provided. To use this
signal, you should set up the UART control register of the AFE interface. For
further information, refer to 13.9 Analog Front End, AFE (CODEC Interface) on
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