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參數(shù)資料
| 型號： | CDK8920A |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | CRYSTAL LAN ISA PLUG-AND-PLAY ETHERNET CONTROLLER |
| 中文描述： | 水晶藍(lán)的ISA即插即用，即插即用以太網(wǎng)控制器 |
| 文件頁數(shù)： | 99/144頁 |
| 文件大?。?/td> | 1229K |
| 代理商： | CDK8920A |
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buffer size is 16 Kbytes. When RxDMAsize is
set, the buffer is 64 Kbytes. It is the host’s task
to locate and keep track of the DMA receive
buffer’s base address. The DMA Start-of-Frame
register is the only circuit affected by this bit.
APPLICATION NOTE: As a result of the PC ar-
chitecture, DMA cannot occur across a 128K
boundary in memory. Thus, the DMA buffer re-
served for the CS8920A must not cross a 128K
boundary in host memory if DMA operation is
desired. Requesting a 64K, rather than a 16K
buffer, increases the probability of crossing a
128K alignment boundary. After the driver re-
quests a DMA buffer, the driver must check for a
boundary crossing. If the boundary is crossed,
then the driver must disable DMA functionality.
5.5.4
Receive-DMA-Only Operation
If space is available, an incoming frame is tem-
porarily stored in on-chip RAM. When the entire
frame has been received, pre-processed, and ac-
cepted, the CS8920A signals the DMA controller
that a frame is to be transferred to host memory
by driving the selected DMA Request pin high.
The DMA controller acknowledges the request
by driving the DMA Acknowledge pin low. The
CS8920A then transfers the contents of the
RxStatus register (PacketPage base + 0400h) and
the RxLength register (PacketPage base + 0402h)
to host memory, followed by the frame data. If
the DMABurst bit (Register 17, BusCTL, Bit B)
is clear, the DMA Request pin remains high until
the entire frame is transferred. If the DMABurst
bit is set, the DMA Request pin (DMARQ) re-
mains high for approximately 28
μ
s then goes
low for approximately 1.3
μ
s to give the CPU
and other peripherals access to the bus.
The CS8920A’s DMA request pin remains active
(HIGH), until all but one word is transferred.
The DMA request pin goes inactive just before
transfer of the last word. For an ISA bus, the
DMA request signal is latched during a DMA
cycle. Therefore, a DMA controller will gener-
ate one more cycle after the CS8920A’s DMA
request pin goes inactive. The CS8920A expects
this additional DMA cycle after its DMA request
pin goes inactive.
When the transfer is complete, the CS8920A
does the following:
updates the DMA Start-of-Frame register
(PacketPage base + 0026h);
updates the DMA Frame Count register
(PacketPage base + 0028h);
updates DMA Byte Count register (Packet-
Page base + 002Ah);
sets the RxDMAFrame bit (Register C,
BufEvent, Bit 7); and,
de-allocates the buffer space used by the
transferred frame.
In addition, if the RxDMAiE bit (Register B,
BufCFG, Bit 7) is set, a corresponding interrupt
occurs.
PacketPage
Address
0374h
Register Description
DMA Channel Number:
DMA channel
number (0, 1, or 2) that defines the
DMARQ/DMACK pin pair used.
DMA Start-of-Frame:
16-bit value that
defines the offset from the DMA base
address to the start of the most recently
transferred received frame.
DMA Frame Count:
The lower 12 bits
define the number of valid frames
transferred via DMA since the last read-out
of this register. The upper 4 bits are
reserved and not applicable.
DMA Byte Count:
Defines the number of
bytes that have been transferred via DMA
since the last read-out of this register.
0026h
0028h
002Ah
Table 5.8. Receive DMA Registers
CS8920A
DS238PP2
99
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