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參數(shù)資料
| 型號(hào)： | CDK8920A |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | CRYSTAL LAN ISA PLUG-AND-PLAY ETHERNET CONTROLLER |
| 中文描述： | 水晶藍(lán)的ISA即插即用，即插即用以太網(wǎng)控制器 |
| 文件頁(yè)數(shù)： | 82/144頁(yè) |
| 文件大?。?/td> | 1229K |
| 代理商： | CDK8920A |
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4.11.1
Accesses in Memory Mode
The CS8920A allows Read/Write access to the
internal PacketPage memory, and Read access of
the optional Boot PROM. (See Section 3.7 for a
description of the optional Boot PROM.)
A memory access occurs when all of the follow-
ing are true:
The address on the ISA System Address bus
SA[0:16] and LA[17:23] is within the Mem-
ory space range of the CS8920A or Boot
PROM.
Either the MEMR pin or the MEMW pin is
low.
4.11.2
Mode
Configuring the CS8920A for Memory
The CS8920A’s internal memory can be mapped
anywhere within the host system’s 24-bit mem-
ory space. The CS8920A occupies 4K bytes of
space in the system memory map. Configuring
the CS8920A to respond in a memory mode re-
quires the following:
The Memory Base Address Registers
(PackatePage base + 0348h and 0349h) should
have the high and low bytes of the 24 bit mem-
ory base address. The value written in register at
0348h must be non-zero for memory mode to be
active. For example, if the memory base address
for the CS8920A is to be 0C8000h, write 0C at
PackatPage base + 0348h and 80h at PacketPage
base + 0349h.
The MemoryE bit (Bit A) in the Bus Control
register (Register 17, PacketPage base + 116h)
must be set.
The CS8920A latches address on pins LA[17:23]
when the BALE signal remains LOW. When
either MEMR (memory read) or MEMW (mem-
ory write) pin goes active (LOW), the CS8920A
will respond to memory access if
Address latched from the LA[17:23] and ad-
dress on pins SA[12:16] match the address in the
Memory Base Address Register, and
The memory enable bit MemoryE bit in the
Bus Control register is set, and
REFRESH, and AEN signals are inactive.
4.11.3
Basic Memory Mode Transmit
Memory Mode transmit operations occur in the
following order (using interrupts):
1.The host bids for storage of the frame by writ-
ing the Transmit Command to the TxCMD
register (memory base + 0144h) and the trans-
mit frame length to the TxLength register
(memory base + 0146h). If the transmit length
is erroneous, the command is discarded and
the TxBidErr bit (Register 18, BusST, Bit 7) is
set.
2.The host reads the BusST register (Register 18,
memory base + 0138h). When the
Rdy4TxNOW bit (Bit 8) is set, the frame can
be written. When clear, the host must wait for
CS8920A buffer memory to become available.
When Rdy4TxiE (Register B, BufCFG, Bit 8)
is set, the host will be interrupted when
Rdy4Tx (Register C, BufEvent, Bit 8) be-
comes set.
3.Once the CS8920A is ready to accept the
frame, the host executes repetitive memory-to-
memory move instructions (REP MOVS) to
memory base + 0A00h to transfer the entire
frame from host memory to CS8920A mem-
ory.
For a more detailed description of transmit, see
Section 5.8.
CS8920A
82
DS238PP2
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